Quadrature Clock Correction for Low-Jitter Phase Rotators
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Solution Overview
Problem
Existing clock generation systems in high data-rate serializer-deserializer (SERDES) applications face challenges in maintaining accurate quadrature relationship and duty cycle of reference clocks due to mismatch errors and temperature variations, leading to significant data sample jitter that exceeds acceptable limits.
Innovation Solution
A closed-loop dynamic clock correction system that adjusts in-phase and quadrature clocks using feedback mechanisms to generate a 4-quadrant interpolated output clock phase, measuring errors over a range of phases, and adapting the clocks to correct duty cycle, quadrature, and amplitude errors, thereby reducing jitter and improving phase linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If open-loop clock buffer methods are used to improve quadrature accuracy and duty cycle, then local clock buffering is simplified, but significant jitter remains that exceeds acceptable limits
Solution Approach 1:
The patent implements a closed-loop feedback system where the output clock is sampled and compared to generate error signals that are fed back to adjust the phase rotator and clock buffer. This feedback mechanism dynamically corrects jitter and maintains quadrature accuracy, resolving the contradiction between simple open-loop buffering and reliable jitter performance.
Solution Approach 2:
The patent replaces traditional mechanical/analog clock buffering with a digital-based system using phase rotators, digital-to-analog converters (DACs), and digital error correction logic. This substitution enables precise digital control of clock phases and dynamic jitter correction, achieving reliable performance while maintaining operational simplicity.
2Measurement precision
If phase rotators are used to generate interpolated output clock phases, then phase resolution is improved, but sensitivity to quadrature clock errors increases
Solution Approach 1:
The closed-loop feedback system continuously monitors the output clock and generates error signals that correct quadrature clock errors in real-time. This feedback compensates for the increased sensitivity of phase rotators to quadrature errors, maintaining high phase resolution while eliminating the harmful effect of error amplification.
Solution Approach 2:
The patent applies preliminary correction to the quadrature clocks before they are used by the phase rotator. The error correction logic pre-adjusts the quadrature clock phases based on measured errors, preventing error propagation to the high-resolution phase interpolation process.
3Device complexity
If a single PLL is used to distribute clocks to multiple I/O cores, then device complexity is reduced, but mismatch errors and temperature variations cause significant jitter
Solution Approach 1:
The patent implements a closed-loop feedback system that dynamically corrects jitter caused by mismatch errors and temperature variations. The feedback mechanism continuously adjusts the clock signals distributed to multiple I/O cores, maintaining reliable jitter performance while preserving the simplicity of the single-PLL architecture.
Solution Approach 2:
The patent dynamically adjusts clock parameters (phase, frequency, duty cycle) using DAC-controlled phase rotators and error correction logic. This parameter adjustment compensates for temperature variations and mismatch errors, achieving reliable jitter performance without increasing device complexity.
4Reliability
If dynamic error correction is implemented to reduce jitter, then reliability is improved, but device complexity increases due to additional correction circuitry
Solution Approach 1:
The patent implements a multi-functional error correction system where the same feedback mechanism corrects multiple types of errors (jitter, quadrature errors, duty cycle errors) simultaneously. This universal correction approach improves reliability without proportionally increasing device complexity, as one system handles multiple correction functions.
Solution Approach 2:
The error correction system is self-regulating, using the output clock itself to generate error signals that automatically adjust the clock parameters. This self-service mechanism reduces the need for external control circuitry and minimizes device complexity while maintaining improved reliability.
Data Source
AI summary
A system and method for closed loop clock correction includes adjusting two or more input signals comprising at least one in-phase clock and one quadrature clock, and applying adjusted quadrature clock signals to a device capable of generating a 4-quadrant interpolated output clock phase. An interpolated output clock phase is delayed to form a clock for a measurement device. Two or more adjusted input signals are measured on a measurement device over a range of interpolated output clock phases. Errors are determined on the in-phase clock and the quadrature clock using sampled information from the measurement device. The in-phase clock and the quadrature clock are adapted using determined error information.