Quadrature Clock Summing Network for Uniform Phase Timing
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Solution Overview
Problem
Existing quadrature clock circuits, such as polyphase filters, require large physical layout areas due to the use of capacitors and resistors, which are less area-efficient in modern integrated circuit fabrication processes like CMOS.
Innovation Solution
A circuit comprising four summing networks that receive and output phases of a quadrature clock, utilizing inverters to achieve an equal sum of input phases, thereby improving timing uniformity without the need for capacitors and resistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a polyphase filter with capacitors and resistors is used to improve quadrature clock accuracy, then the timing uniformity of the four phases is improved, but the physical layout area occupied by the circuit increases
Solution Approach 1:
The invention changes the fundamental parameters of the circuit by replacing capacitors and resistors with current sources and summing networks. This parameter substitution maintains the timing uniformity function while dramatically reducing the physical area required, as current sources and summing networks are much more area-efficient in CMOS fabrication processes
Solution Approach 2:
The invention substitutes the passive RC (resistor-capacitor) mechanical/electrical system with an active current-based system. By using current sources to generate phase signals and summing networks to combine them, the circuit achieves the same timing correction function without requiring large physical capacitors and resistors
Data Source
AI summary
A circuit and method are provided for improving the accuracy of a quadrature clock. The method includes receiving a first phase, a second phase, a third phase, and a fourth phase of a first quadrature clock; outputting a first phase of a second quadrature clock in accordance with an equal sum of the first phase and the second phase of the first quadrature clock using a first summing network; outputting a second phase of the second quadrature clock in accordance with an equal sum of the second phase and the third phase of the first quadrature clock using a second summing network; outputting a third phase of the second quadrature clock in accordance with an equal sum of the third phase and the fourth phase of the first quadrature clock using a third summing network; and outputting a fourth phase of the second quadrature clock in accordance with an equal sum of the fourth phase and the first phase of the first quadrature clock using a fourth summing network.