Quadrature Clock Generation Using Rise-Fall Duty Cycle Correction
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Solution Overview
Problem
Conventional circuits for generating quadrature clock signals require a reference clock with twice the frequency of the desired quadrature clock signals, leading to high power consumption and complexity, and struggle to accurately maintain phase offset and duty cycle, resulting in inaccurate clock signals.
Innovation Solution
The proposed solution involves a quadrature clock generator that uses an in-phase clock generation circuit and a quadrature phase clock generation circuit, with a control circuit to generate rise time and fall time control signals based on the in-phase and quadrature clock signals, allowing for accurate phase offset and duty cycle adjustment without requiring a double frequency reference clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a reference clock with twice the frequency is used to generate quadrature clock signals, then the phase offset can be maintained, but power consumption and circuit complexity increase
Solution Approach 1:
The patent changes the frequency parameter of the reference clock from twice the desired quadrature frequency to the same frequency as the desired output. This parameter change allows the system to generate quadrature signals at the target frequency directly, avoiding the need for high-frequency reference clocks and thereby reducing power consumption while maintaining phase accuracy through control circuits.
Solution Approach 2:
The patent introduces control circuits as intermediary components that receive the same-frequency reference clock and generate quadrature clock signals with accurate phase offsets. These control circuits act as mediators that enable precise phase control without requiring the reference clock to operate at twice the output frequency, thus resolving the contradiction between phase accuracy and power consumption.
2Measurement precision
If a reference clock with twice the frequency is used, then quadrature signals can be generated, but device complexity increases
Solution Approach 1:
By changing the reference clock frequency parameter from 2x to 1x the desired output frequency, the patent simplifies the overall device architecture. The control circuits process the lower-frequency reference clock to generate quadrature signals, reducing the complexity associated with handling and distributing high-frequency reference clocks throughout the system.
3Productivity
If conventional circuits are used to generate quadrature clocks, then clock signals can be produced, but duty cycle accuracy deteriorates
Solution Approach 1:
The patent implements feedback mechanisms within the control circuits that monitor and adjust the duty cycle of generated quadrature clock signals. This feedback ensures that despite using a same-frequency reference clock instead of a double-frequency reference, the duty cycle remains accurate by continuously correcting deviations through the control logic.
Data Source
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AI summary
Quadrature clock generation circuits and techniques are disclosed. An example quadrature clock generator includes an in-phase (I) clock generation circuit to generate an I clock signal based on a reference clock signal, the I clock signal and the reference clock signal each having a first frequency, a quadrature phase (Q) clock generation circuit to generate a Q clock signal based on the reference clock signal, a rise time control signal, and a fall time control signal, the Q clock signal having the first frequency, and a control circuit to generate the rise time control signal and the fall time control signal based on the I clock signal and the Q clock signal.