Quadrature Clock Correction Circuit for Skew and Duty Cycle Errors
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Solution Overview
Problem
Semiconductor memory devices face challenges in concurrently correcting clock signal skew and duty cycle errors, which affect the synchronization and performance of memory operations.
Innovation Solution
A quadrature error correction circuit is implemented, comprising a duty cycle adjusting circuit, phase splitters, a phase interpolator, and a delay control circuit, which adjusts the phase and delay of clock signals to concurrently correct skew and duty cycle errors, generating corrected clock signals with a 90-degree phase difference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional clock signal correction circuit is used, then either skew or duty cycle can be corrected, but not both concurrently
Solution Approach 1:
The correction circuit is divided into separate functional modules: a duty cycle correction unit that adjusts the duty cycle of clock signals, and a skew correction unit that adjusts the phase relationship between differential clock signals. Each module independently handles its specific correction task, allowing both skew and duty cycle to be corrected concurrently without interference.
Solution Approach 2:
The correction circuit is designed to perform multiple functions simultaneously: it corrects both the duty cycle error of individual clock signals and the skew between differential clock signals. This multi-functional approach enables a single circuit to address all clock signal errors, improving both reliability and versatility.
2Reliability
If multiple separate correction circuits are used for skew and duty cycle, then correction capability is improved, but device complexity increases
Solution Approach 1:
The duty cycle correction unit and skew correction unit are merged into a single integrated correction circuit. The circuit receives differential clock signals and processes both duty cycle adjustment and skew correction within the same structural framework, reducing the number of separate components while maintaining comprehensive correction capability.
Solution Approach 2:
The correction circuit is designed as a universal unit that handles multiple types of clock signal errors (duty cycle error and skew) simultaneously. This multi-functional design eliminates the need for separate correction circuits for each error type, thereby reducing overall device complexity while maintaining high correction accuracy.
Data Source
AI summary
A quadrature error correction circuit includes a duty cycle adjusting circuit, a phase interpolator, a phase detector, and a delay control circuit. The duty cycle adjusting circuit generates a first corrected clock signal and a second corrected clock signal whose skew and duty cycle error are concurrently adjusted by adjusting a delay of edges of a second clock signal and adjusting a delay of a falling edge of a first clock signal based on first through fourth control code sets. The phase interpolator generates a second delayed and selected clock signal by delaying a second selected clock signal selected from first through fourth adjusted clock signals. A phase detector detects a phase difference between a first selected clock signal and the second delayed and selected clock signal to generate an up/down signal. The delay control circuit generates the first through fourth control code sets based on the up/down signal.