Memory Interface Quadrature Clock Adjustment for Skewed Timing
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Solution Overview
Problem
Digital systems face clock signal skew due to propagation delays, leading to phase desynchronization across different clock paths, which reduces timing margins for data recognition windows.
Innovation Solution
The implementation of clock phase adjuster circuits with controllable delay elements and voltage regulators in memory controllers and memory circuits, allowing for incremental phase adjustments of clock signals to maintain synchronization across multiple paths within a clock tree.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock signals are distributed along multiple paths in a clock tree, then system performance and parallel operations are improved, but propagation delays cause clock signals to skew and timing margins are reduced
Solution Approach 1:
The patent applies local quality by providing each clock path with an independent delay adjustment circuit that can be individually calibrated. This allows each branch of the clock tree to have customized delay compensation, ensuring that clock signals arrive at their destinations simultaneously despite different path lengths and propagation characteristics.
Solution Approach 2:
The patent changes the delay parameter of clock signals dynamically by adjusting the delay adjustment circuits. By modifying the delay characteristics of individual clock paths based on measured skew, the system maintains synchronized clock edges across all paths, thereby preserving timing margins while enabling parallel operations.
2Manufacturing precision
If delay adjustment circuits are added to each clock path, then clock signal phase synchronization is improved, but device complexity increases
Solution Approach 1:
The patent segments the clock distribution system into independent adjustable units, where each clock path has its own delay adjustment circuit. This modular approach allows for precise local control of clock phases while keeping each adjustment unit relatively simple in structure, thus managing overall system complexity through functional decomposition.
Solution Approach 2:
The delay adjustment circuits are configured to automatically calibrate themselves by detecting clock skew and adjusting their delay characteristics accordingly. This self-service capability reduces the need for complex external control mechanisms, thereby improving phase synchronization without proportionally increasing device complexity.
Data Source
AI summary
A system is provided with clock skew measurement and correction technology. A first circuit or memory controller 4 includes measuring circuits to measure relative timing or phase offsets of multiple clock signals of a second circuit or memory 6. One measuring circuit is configured for incremental changing of the phase of a transmitted test data sequence to measure and correct timing of a memory receiver circuit's quadrature clocks based on results of a data comparison of transmitted and received test data. Another measuring circuit is configured to scan a received test data sequence for data transitions to measure and correct timing of a memory transmitter circuit ' s quadrature clocks based on spacing or timing between detected transitions. Individual memory clock generators 30 are controlled with adjustable delay circuits 47 for changing phase of different clock signals of the memory to set the clock signals based on the measurements of the controller.