Quadrature Clock Delay Cell With PVT Tracking and Edge Symmetry
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Solution Overview
Problem
Conventional delay circuits are susceptible to process, voltage, and temperature (PVT) variations, leading to instability in delay performance, which is inadequate for modern semiconductor applications requiring high precision and insensitivity across various conditions.
Innovation Solution
A delay circuit design incorporating a first N-substage with a sinking current source and a first P-substage with a sourcing current source, both variable with bias voltages, along with a duty cycle correction module and tracking modules to adjust edges and compensate for PVT variations, ensuring robustness and equal rising and falling edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional delay circuits are used, then the circuit structure is simple, but the delay performance is sensitive to PVT variations
Solution Approach 1:
The delay circuit is divided into separate N-substage and P-substage, each handling specific edge transitions. This segmentation allows independent optimization of each substage to compensate for PVT variations, improving delay stability without requiring complete circuit redesign.
Solution Approach 2:
The circuit uses variable bias voltages (Vbn, Vbp) to dynamically adjust the operating parameters of the current sources. By changing these bias parameters, the delay circuit can compensate for PVT variations and maintain stable performance across different process, voltage, and temperature conditions.
2Manufacturing precision
If conventional delay circuits are used, then the circuit is simple, but the rising and falling edges are unequal
Solution Approach 1:
The circuit separates rising edge generation (N-substage) from falling edge generation (P-substage), allowing each to be independently optimized. This enables precise control over edge characteristics to achieve equal rising and falling edges, which would be difficult in a unified conventional design.
Solution Approach 2:
The circuit employs asymmetric current source design with different transistor configurations for N-substage and P-substage. This intentional asymmetry compensates for inherent process variations that cause unequal edges, allowing each substage to be tuned for optimal edge equality.
3Reliability
If delay circuits are made insensitive to PVT variations, then delay stability is improved, but the circuit complexity increases
Solution Approach 1:
The circuit incorporates feedback mechanisms where the bias voltages are adjusted based on detected delay variations. This feedback allows the circuit to automatically compensate for PVT variations, achieving PVT insensitivity through continuous adjustment rather than complex static design.
Solution Approach 2:
The circuit transitions from static delay elements to dynamic delay elements with adjustable bias voltages. This dynamics allows the circuit to adapt to changing PVT conditions in real-time, achieving insensitivity through adaptability rather than through complex fixed-structure design.
4Measurement precision
If extensive calibration ranges are used, then delay precision is improved, but the calibration complexity and time increase
Solution Approach 1:
The circuit uses a limited set of bias voltage parameters (Vbn, Vbp) that can be adjusted to cover the required calibration range. This parameter-based approach allows precise delay adjustment without requiring extensive calibration steps, reducing calibration time while maintaining high precision.
Data Source
AI summary
A novel delay circuit for quadrature clock generation with insensitivity to process, voltage, temperature (PVT) variations and equal rising/falling edges is disclosed. In one implementation, the delay circuit includes a first N-substage having a sinking current source, configured to receive an input signal and to generate a rising edge of an output signal of the delay circuit, wherein the output signal is a delayed version of the input signal. The delay circuit further includes a first P-substage having a sourcing current source, configured to receive the input signal and to generate a falling edge of the output signal, where the sinking current source and the sourcing current source are variable in response to respective ones of a plurality of bias voltages.