Quadrature Divider Phase Correction for Sub-Rate Clock Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern electronic devices face challenges in synchronizing multiple frequency clock dividers due to clock signal spacing errors, which affect the timing precision of sub-rate clocks, especially in high-speed data communication systems, leading to increased jitter and power consumption in PLL cores.
Innovation Solution
A system comprising a frequency divider, phase detector, low pass filter, and control unit that corrects clock signal spacing errors by generating control signals to adjust the input clock signals, utilizing a quadrature divider with flip flops and latches to produce output clock signals with precise frequency division and timing alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If frequency division is performed using traditional dividers, then frequency reduction is achieved, but clock signal spacing errors occur leading to timing misalignment
Solution Approach 1:
The patent implements a feedback mechanism where the output clock signals are fed back to a phase detector that compares their phases. The phase detector generates error signals based on phase differences, which are then used to adjust the input clock signals through a control unit. This closed-loop feedback system continuously corrects spacing errors, ensuring precise timing alignment while maintaining frequency division functionality.
Solution Approach 2:
The patent replaces traditional mechanical or simple digital frequency division mechanisms with an electronic control system involving phase detectors, low-pass filters, and control units. This substitution allows for dynamic adjustment and correction of clock signal spacing through electronic feedback, achieving higher precision than fixed mechanical dividers could provide.
2Adaptability or versatility
If multiple frequency dividers are used to achieve different clock frequencies, then functional versatility is improved, but synchronization complexity increases
Solution Approach 1:
The patent creates a universal frequency division system where multiple output clocks are generated from a single input clock through one unified divider circuit. The phase detector and control unit serve all output clocks simultaneously, making the system adaptable to different frequency requirements while maintaining synchronization through a single control mechanism rather than separate synchronization circuits for each divider.
Solution Approach 2:
The patent merges multiple frequency division operations into a single integrated system. Instead of using separate dividers that would each require independent synchronization, the invention combines the division function with a unified phase detection and control mechanism that manages all output clocks together, reducing overall system complexity.
3Device complexity
If clock signal spacing errors are not corrected, then system simplicity is maintained, but jitter and power consumption increase
Solution Approach 1:
The patent employs feedback control where phase detectors continuously monitor output clock signals and generate correction signals based on detected phase errors. These feedback signals are processed through low-pass filters and control units that adjust the input clocks in real-time, minimizing jitter and maintaining timing precision without requiring overly complex correction circuits.
Solution Approach 2:
The system implements self-correction capability where the frequency divider automatically detects and corrects its own spacing errors through the integrated phase detector and control unit. The system monitors its own output and adjusts its operation accordingly, eliminating the need for external correction mechanisms while maintaining high reliability.
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
A circuit including a frequency divider configured to receive a plurality of first frequency input clock signals and provide a plurality of second frequency output clock signals, wherein the plurality of second frequency output clock signals are lower in frequency than the plurality of first frequency input clock signals, a phase detector configured to determine a difference between the plurality of second frequency output clock signals, a low pass filter configured to measure a clock signal spacing error associated with the plurality of second frequency output clock signals based on the difference between the plurality of second frequency output clock signals and to generate one or more control signals in response to the clock signal spacing error, and a control unit configured to generate one or more corrected first frequency input clock signals based on the one or more control signals.