Non-Sequential Quadrature Error Correction for Memory Devices
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Solution Overview
Problem
Existing memory devices face challenges in accurately correcting phase errors in quadrature clocks due to process variations and mismatches, leading to inefficiencies in data transmission and storage, which can result in errors and reduced performance.
Innovation Solution
A memory device and system that utilize a non-sequential quadrature error correction method, employing a single phase detector and delay lines to simultaneously detect and correct phase errors in a quadrature clock, reducing lock time and chip size while maintaining accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sequential phase error correction is used, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The phase error correction process is segmented into multiple independent detection cycles, where each cycle detects phase errors between adjacent clocks (I-Q, Q-IB, IB-QB, QB-I). This segmentation allows parallel processing of different phase comparisons, reducing the total lock time while maintaining detection accuracy through systematic sequential updates of delay codes.
Solution Approach 2:
The system performs preliminary phase error detection across all clock pairs in succession, accumulating phase difference information before final correction. This preliminary action allows the system to prepare correction data in advance, reducing the actual lock time required while ensuring accurate phase error measurement through comprehensive preliminary detection.
2Measurement precision
If multiple phase detectors are used, then measurement precision is improved, but device complexity increases
Solution Approach 1:
A single phase detector is designed to perform multiple functions by sequentially detecting phase errors between different clock pairs (I-Q, Q-IB, IB-QB, QB-I). The phase detector is reused in each detection cycle with different clock inputs, eliminating the need for multiple dedicated phase detectors while maintaining comprehensive phase error detection capability across all clock relationships.
Solution Approach 2:
The single phase detector serves itself by being reused across multiple detection cycles with different clock inputs. Instead of requiring separate detectors for each clock pair, the same detector component performs all phase error measurements through systematic reconfiguration, reducing device complexity while maintaining measurement precision through self-service operation.
3Manufacturing precision
If delay line updates are performed sequentially, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
The delay code update process is segmented into discrete phases corresponding to each clock pair detection (I-Q, Q-IB, IB-QB, QB-I). Each segment updates the appropriate delay code based on its specific phase error measurement, allowing systematic precision control for each delay line while enabling parallel progression through multiple segments, thereby improving both manufacturing precision and correction productivity.
Solution Approach 2:
The delay line updates continue continuously across multiple detection cycles without interruption. While one delay code is being updated based on phase error detection, the system immediately proceeds to detect and update the next delay code in sequence. This continuous useful action ensures that all delay lines are progressively corrected without idle time, maintaining high productivity while achieving accurate delay code adjustment for each clock pair.
Data Source
AI summary
A method of operating a memory device includes receiving a quadrature clock and performing quadrature error correction of the quadrature clock in a non-sequential scheme, wherein the quadrature clock includes a first clock, a second clock, a third clock, and a fourth clock, having a sequential phase.