Quadrature Frequency Multiplier Circuit With Low Spurious Harmonics
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Solution Overview
Problem
Conventional frequency quadruplication systems face challenges such as high architectural complexity, the use of high-complexity components, high supply voltage requirements, and the generation of spurious harmonics, which degrade performance and efficiency.
Innovation Solution
A method and circuit using dual balanced frequency doublers driven in quadrature by a 90° phase shifter, employing a single balanced doubler to generate a sinusoidal signal with broad band characteristics, suppressing undesired fundamental and doubled frequency harmonic components, and avoiding cascading doublers that produce spurious harmonics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional cascaded frequency doubling stages are used, then high frequency signals can be generated, but spurious harmonics are generated and system complexity increases
Solution Approach 1:
The frequency multiplication function is segmented into two independent parallel doubler stages instead of a single cascaded chain. Each doubler operates independently at the fundamental frequency, generating 2nd harmonics that are then combined to produce the 4th harmonic, avoiding the accumulation of spurious harmonics from cascaded stages.
Solution Approach 2:
The output signals from two independent doubler stages are merged at a combining node. The 2nd harmonics from both doublers are combined constructively to generate the desired 4th harmonic output, while filtering removes unwanted components, achieving frequency quadruplication with reduced spurious content.
2Power
If multiple amplification stages are added to recover signal power, then output power is maintained, but device complexity and power consumption increase
Solution Approach 1:
Multiple signal paths (two doubler stages) are merged at a common output node, combining their power contributions to achieve the required output power level. This merging approach naturally recovers power without requiring additional amplification stages, reducing overall device complexity.
3Reliability
If high frequency filters are added to eliminate spurious harmonics, then signal purity is improved, but device complexity increases
Solution Approach 1:
The harmful spurious harmonic components are extracted and removed from the signal path using a high frequency filter at the output. By placing a single filter at the final output stage rather than multiple intermediate filters, signal purity is achieved with minimal added complexity.
4Reliability
If impedance matching stages are added between cascaded doublers, then performance is maintained, but architectural complexity increases
Solution Approach 1:
The system is segmented into two independent parallel doubler stages rather than a cascaded configuration. This segmentation eliminates the need for intermediate impedance matching stages between doublers, as each doubler operates independently and connects directly to the combining node, simplifying the overall architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a compact, high-performance frequency multiplier with improved radio-frequency component efficiency, reduced power consumption, and minimal spurious harmonics, suitable for broad-band applications.
Implementation Method 1
a phase-shifter network (210), coupled to the input port and configured to receive the input signal and to provide a set of out-of-phase signals
Implementation Method 2
a first frequency doubler (220a) configured to receive the first signal and to provide as output a first rectified signal having a second frequency value twice the first frequency value
Implementation Method 3
a common node (S) configured to receive and combine the set of rectified signals, providing a combined signal having a harmonic component at a frequency fourfold the input signal frequency
Data Source
AI summary
A circuit includes an input port receiving an input signal having a first frequency. A phase-shifter network is coupled to the input port, receives the input signal, and produces therefrom first and second signals in quadrature with one another. Frequency multiplier circuitry has a common node and includes a first rectifier for rectifying the first signal to produce a first rectified signal having a second frequency that is twice the first frequency and to be applied to the common node, and a second rectifier rectifying the second signal to produce a second rectified signal having the second frequency and to be applied to the common node. A combination of the first and second rectified signals is available at the common node and includes harmonic contents at a frequency that is fourfold the first frequency.