Quadrature Generator Circuit With Lower Clock Buffer Loading
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Solution Overview
Problem
Modern mobile wireless communication devices face challenges in reducing power consumption while maintaining performance, particularly in quadrature generator circuits which contribute to overall device power usage.
Innovation Solution
The proposed solution involves a novel quadrature waveform generator circuit configuration using a frequency divider and output circuits comprising specific transistor configurations to reduce capacitive loading on clock buffers, thereby minimizing power consumption without compromising performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional quadrature generator circuit configuration is used, then performance is maintained, but power consumption is high
Solution Approach 1:
The patent extracts and removes unnecessary capacitive loading elements from the conventional quadrature generator circuit. By eliminating redundant capacitors and reducing capacitive loads on clock buffers, the circuit achieves lower power consumption while preserving the essential quadrature signal generation function.
Solution Approach 2:
The patent changes key circuit parameters including reducing capacitive load values, modifying transistor configurations, and adjusting circuit topology. These parameter changes optimize the balance between power consumption and performance, achieving 3-4% current drain reduction while maintaining signal integrity.
2Loss of energy
If number of transistors is reduced, then power consumption decreases, but circuit functionality may be compromised
Solution Approach 1:
The patent merges multiple transistor functions into more efficient configurations. By combining certain transistor operations and optimizing the transistor network topology, the circuit achieves reduced transistor count and lower current drain while maintaining all necessary quadrature generation functions.
Solution Approach 2:
The patent employs dynamic transistor switching strategies where transistors are activated only when needed for specific signal paths. This dynamic approach reduces the effective transistor count during operation, lowering power consumption while ensuring all circuit functions remain available when required.
3Use of energy by moving object
If capacitive loading on clock buffers is reduced, then power consumption decreases, but signal quality may be affected
Solution Approach 1:
The patent carefully optimizes capacitive loading parameters to find the optimal balance point. By adjusting capacitor values and distributed capacitance to specific optimal levels, the circuit achieves reduced power consumption while maintaining phase noise performance within acceptable thresholds.
Solution Approach 2:
The patent incorporates feedback mechanisms that monitor signal quality and adjust capacitive loading dynamically. This feedback control ensures that power consumption is minimized while phase noise and signal quality remain within specified performance boundaries.
Data Source
AI summary
An apparatus comprising a frequency divider comprising a first latch and a second latch coupled to the first latch in a toggle-flop configuration, and an output circuit comprising a first p-channel transistor, wherein the gate of the first p-channel transistor is configured to receive a clock signal, a first n-channel transistor, wherein the gate of the first n-channel transistor is coupled to the first latch, a second n-channel transistor connected in series with the first p-channel transistor and the first n-channel transistor and wherein the gate of the second n-channel transistor is configured to receive the clock signal, a second p-channel transistor, wherein the gate of the second p-channel transistor is configured to receive the clock signal, and a third n-channel transistor in series with the second p-channel transistor and the second n-channel transistor, wherein the output circuit is configured to generate a pair of in-phase reference signals.