Quadrature Passive Mixer Clocking for High Linearity RF Receivers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Direct conversion receivers in RF communication systems face challenges with high noise figure and power consumption due to active mixers, particularly in narrow band applications, and achieving high linearity is difficult with conventional four-phase clock schemes, which also lead to increased power consumption and distortion.
Innovation Solution
A wireless transceiver design using a quadrature mixer with in-phase and quadrature-phase passive mixers driven by distinct clock signals, where the VCO clock signals have twice the frequency of the LO clock signals, allowing for a wider duty cycle and reduced jitter influence, improving linearity and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If active mixers are used to provide gain in direct conversion receivers, then signal amplification is achieved, but noise figure increases due to flicker noise and power consumption increases
Solution Approach 1:
The patent employs passive mixers instead of active mixers, sacrificing the gain function but eliminating flicker noise and reducing power consumption. The passive mixer architecture uses switching elements that consume minimal power and do not generate flicker noise, accepting the trade-off of requiring a stronger input signal or additional gain stages elsewhere in the receiver chain.
2Manufacturing precision
If conventional four-phase clock schemes are used to achieve high linearity, then IIP2 performance improves, but duty cycle becomes narrow (less than 25%) making clock driver design difficult and power consumption increases
Solution Approach 1:
The patent dynamically adjusts the clock signal characteristics by using a differential clocking scheme where the clock signals have a duty cycle between 25% and 50%, optimized for both linearity and power efficiency. The system adapts the clock waveform shape and timing to maintain non-overlapping phases while achieving the desired linearity performance without excessive power consumption.
Solution Approach 2:
The patent changes the clock signal parameters by using a differential four-phase clocking scheme with specific duty cycle optimization. The clock signals are designed to have rising and falling edges that are properly timed to achieve high linearity while maintaining a practical duty cycle that simplifies clock driver design and reduces power consumption compared to conventional narrow-duty-cycle schemes.
3Manufacturing precision
If bias voltage of sinusoidal clock signals is increased to achieve higher gate over-drive for better linearity, then mixer linearity improves, but clock signals overlap adversely affecting mixer functionality
Solution Approach 1:
The patent uses dynamic clock signal generation with differential four-phase clocking where the timing and amplitude of clock signals are precisely controlled to provide sufficient gate over-drive for linear operation without causing overlap. The system dynamically adjusts the clock waveform characteristics to maintain the non-overlapping condition while achieving the necessary over-drive voltage for optimal linearity.
Solution Approach 2:
The patent introduces differential clocking as an intermediary mechanism that mediates between the need for high gate over-drive and the requirement to prevent clock signal overlap. The differential signaling approach allows independent control of the clock phases and amplitudes, enabling optimization of over-drive voltage without compromising the non-overlapping timing condition.
4Manufacturing precision
If more clock driver stages are used to maintain desired duty cycle in four-phase clock schemes, then clock signal quality improves, but energy consumption increases and edge alignment becomes difficult
Solution Approach 1:
The patent optimizes the clock driver architecture by changing the signaling approach to differential four-phase clocking with optimized duty cycle parameters. This reduces the number of clock driver stages required while maintaining accurate duty cycle control and edge alignment. The differential approach improves signal quality by providing better noise immunity and more precise timing control with fewer stages.
Data Source
AI summary
According to one embodiment, a radio frequency receiver includes a quadrature mixer for converting radio frequency signals to baseband signals or intermediate frequency signals. The quadrature mixer includes an in-phase passive mixer and a quadrature-phase passive mixer. Each passive mixer includes a mixer core having a plurality of mixer input switch transistors and a plurality of output switch transistors connected to the mixer input switch transistors. Clock circuitry generates a first set of clock signals and a second set of clock signals. The first set of clock signals has a frequency twice that of the second set of clock signals. The first set of clock signals is arranged to drive the mixer input switch transistors and the second set of clock signals is arranged to drive the output switch transistors.