Quadrature Resolver Clock Recovery for Asynchronous Data
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Solution Overview
Problem
Existing methods for recovering asynchronous data into a fixed clock domain often require phase-locked loops (PLLs) with analog components like phase detectors and voltage-controlled oscillators (VCOs, which suffer from jitter and false lock issues, necessitating complex design considerations and additional processing to synchronize with a system clock.
Innovation Solution
A circuit using a quadrature resolver with sine and cosine oscillators, multipliers, low-pass filters, and an adder to recreate the dominant frequency of the input data stream without analog components, allowing data recovery on a single clock domain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase-locked loop (PLL) is used to recover data from an asynchronous input stream, then the data can be synchronized to a system clock, but the system requires analog components (phase detectors and VCOs) that suffer from jitter and false lock issues, increasing device complexity and reducing reliability
Solution Approach 1:
The patent replaces the mechanical/analog PLL system with a digital signal processing system. Instead of using analog phase detectors and VCOs, the invention uses digital correlation techniques with sine and cosine oscillators, multipliers, and low-pass filters to achieve the same frequency locking and phase detection functions in the digital domain, thereby eliminating analog component-related reliability issues
Solution Approach 2:
The patent changes the operating parameters by using quadrature oscillators (sine and cosine) at the expected input frequency and processing them through digital multipliers and low-pass filters. This parameter change allows the system to lock onto the dominant frequency of the asynchronous input stream and recover data without requiring analog components, thus improving reliability while maintaining functionality
2Reliability
If a PLL is used to generate a recovered clock synchronous to the input stream, then data recovery is enabled, but the recovered clock frequency differs from the system master clock frequency, requiring additional processing and reducing ease of operation
Solution Approach 1:
The patent replaces the traditional PLL clock generation mechanism with a digital correlation-based frequency detection system. By using digital oscillators and correlation processing, the system can directly identify and lock onto the dominant frequency of the asynchronous input stream, enabling data recovery while providing clear frequency information that can be used to synchronize with the system clock without complex additional processing
Solution Approach 2:
The patent creates a multi-functional digital signal processing system that simultaneously performs frequency detection, phase detection, and data recovery functions. The same digital correlation circuitry used to lock onto the input frequency also provides the recovered data, eliminating the need for separate clock generation and synchronization circuits, thus improving ease of operation
3Reliability
If traditional phase detectors are used in the PLL, then frequency locking is achieved, but jitter and false lock conditions occur, degrading measurement precision and reliability
Solution Approach 1:
The patent replaces analog phase detectors with digital correlation-based phase detection. By using digital multipliers to compute the product of the input signal with quadrature oscillators and then applying low-pass filtering, the system achieves accurate phase and frequency detection without the jitter and false lock problems inherent in analog phase detectors, thereby improving both reliability and measurement precision
Solution Approach 2:
The patent introduces digital low-pass filters as intermediaries between the multiplication stage and the final detection output. These filters smooth the multiplied signals to accurately extract the phase and frequency information without being affected by high-frequency noise or harmonics that could cause false lock conditions, thus improving measurement precision while maintaining reliable frequency locking
Data Source
AI summary
Described herein is an apparatus for the recovery of asynchronous data into a fixed clock domain. A phase-locked loop (PLL) of the known art is replaced by a modified quadrature resolver, and the output from the resolver re-creates the selected frequency component of the input asynchronous data. The zero-crossings of this re-created data clock are used to sample the input data stream. One advantage of this technique is that it operates as a state machine on a single clock, and no analog components such as phase detectors or VCOs are needed. In another embodiment, the samples from the input data stream are changed from pulses to Gaussians, allowing for conversion of the sample rate from one clock domain to another.