Quadrature Sampling Error Compensation in Communication Units
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Solution Overview
Problem
Current wireless communication systems face significant challenges in maintaining signal integrity due to IQ imbalances in quadrature paths, particularly in high-order modulation schemes and wide bandwidth applications, which affect signal-to-noise ratios and error vector magnitude, and existing correction methods are either computationally complex or insufficiently robust.
Innovation Solution
A communication unit and method that employs a switchable analog loop back path to estimate and compensate for quadrature sampling errors by generating test signals and using interpolation filters to adjust clock signals, thereby isolating and correcting sampling errors between ADC and DAC 'I' and 'Q' paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If adaptive statistical estimation techniques are used to correct IQ imbalances, then IQ imbalance correction is achieved, but computational complexity increases and convergence rates become unacceptably slow
Solution Approach 1:
The patent extracts the sampling error estimation function from the complex adaptive statistical estimation process. By using a dedicated circuit to measure the difference in sampling times between I and Q paths and directly calculating the error based on known signal properties, the solution removes the need for complex adaptive algorithms while maintaining correction effectiveness.
Solution Approach 2:
The patent replaces the computational/statistical estimation mechanism with a direct electrical measurement approach. The sampling error is measured electrically through the loop-back path and converted to a timing adjustment signal, substituting complex computational processes with a more straightforward electrical measurement and correction system.
2Productivity
If higher-order modulation schemes or higher IQ bandwidth are employed, then communication capacity is improved, but IQ imbalance impact becomes more acute and TX EVM deteriorates
Solution Approach 1:
The patent applies preliminary action by measuring and compensating for sampling errors before they affect the communication signal. The loop-back path allows pre-characterization of the sampling error in the I and Q paths, enabling timing adjustments to be made in advance that prevent EVM degradation in high-order modulation schemes.
Solution Approach 2:
The patent implements feedback through the loop-back path that feeds measured sampling error information back to the timing adjustment circuit. This closed-loop system continuously monitors and corrects sampling errors, maintaining TX EVM performance even as communication capacity increases with higher-order modulation.
3Ease of manufacture
If residual delay error exists between clock edges in ADC I and Q paths, then circuit implementation is simplified, but sampling error between components increases
Solution Approach 1:
The patent introduces an intermediary measurement system using the loop-back path and timing adjustment circuit. This intermediary mechanism measures the actual sampling error caused by clock edge delays and converts it into a correction signal, allowing the system to account for manufacturing simplifications while achieving precise sampling alignment.
Data Source
AI summary
A communication unit comprises a modem configured to generate a first and second test digital quadrature signal. The modem is configured to: estimate a first sampling error performance associated with a first quadrature path from the first received test digital quadrature signal; estimate a second sampling error performance associated with a second quadrature path from the second received test digital quadrature signal; and generate at least one sampling error compensation signal based on the first estimated sampling error performance and second estimated sampling error performance to be applied to at least one of the receiver and transmitter.