Quadrature TIA DC Offset Calibration for Interdependent I/Q Channels

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Solution Overview

Problem

Conventional DC offset correction methods in quadrature receivers are rendered ineffective due to interdependence between in-phase and quadrature channels, limiting dynamic range and requiring improved calibration techniques.

Innovation Solution

A DC offset calibration circuit that independently determines and calibrates the I-channel and Q-channel DC offsets using a successive approximation technique, facilitated by a hardware sequencer and seed values stored in non-volatile memory, allowing for rapid convergence and compensation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional DC offset correction methods are used in quadrature receivers, then the correction may work in independent channels, but the interdependence between I and Q channels renders such methods futile

Engineering Contradiction:

ImproveDC offset correction effectivenessVSAvoidchannel interdependence

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the DC offset calibration process into independent iterative steps for I-channel and Q-channel, where each channel is calibrated separately while holding the other constant, breaking the interdependence into manageable sequential operations

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements a dynamic iterative calibration process that alternates between calibrating I-channel and Q-channel multiple times, allowing the system to converge to optimal values despite initial interdependence, rather than using a static single-step correction

Inventive Principle:

Principle #15Dynamics

2Measurement precision

If DC offset calibration is performed without seed values, then accurate compensation can be achieved, but calibration time becomes excessively long

Engineering Contradiction:

ImproveDC offset compensation accuracyVSAvoidcalibration time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs preliminary DC offset calibration during factory testing and stores the resulting seed values in non-volatile memory, so that during normal operation the device can quickly retrieve and apply these pre-determined offset values, significantly reducing calibration time while maintaining accuracy

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system uses its own factory-calibrated seed values stored in non-volatile memory to rapidly self-correct DC offsets during operation, eliminating the need for lengthy real-time calibration procedures

Inventive Principle:

Principle #25Self-service

3Productivity

If DC offsets are not corrected in the receiver chain, then dynamic range is maintained, but DC offsets are gained up by subsequent stages limiting dynamic range

Engineering Contradiction:

Improvesignal processing gainVSAvoidDC offset amplification

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent extracts and corrects DC offset components at the TIA output stage before they enter the high-gain baseband processing chain, removing the harmful DC offsets that would otherwise be amplified by subsequent stages and limit dynamic range

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS20250309827A1DC offset calibration in an interdependent quadrature receiver

Publication Date: 2025.10.02 SILICON LABORATORIES INC

AI summary

In one aspect, an apparatus includes: a low noise amplifier (LNA) to receive and amplify a radio frequency (RF) signal; a mixer coupled to the LNA to downconvert the RF signal to a second frequency signal; a quadrature transimpedance amplifier (TIA) to convert a current of the second frequency signal to a voltage signal, the quadrature TIA having an in-phase (I)-channel having an I-channel DC offset and a quadrature-phase (Q)-channel having a Q-channel DC offset; and a DC offset calibration circuit coupled to the quadrature TIA. The DC offset calibration circuit is configured to calibrate a DC offset of the quadrature TIA. The DC offset calibration circuit may be configured to independently determine an I-channel DC offset setting and independently determine a Q-channel DC offset setting, where the I-channel and Q-channels have a DC offset interdependency.