Quadruple Patterning Spacer Sacrificial Layers
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Solution Overview
Problem
Current semiconductor manufacturing techniques, such as photo-exposure equipment, face limitations in forming patterns with line widths smaller than 40 nm, and quadruple patterning technologies struggle to ensure pattern fidelity and space uniformity due to unstable partition pattern profiles.
Innovation Solution
A method involving repeated spacer patterning processes is modified by forming spacer sacrificial layers through thermal oxidation, allowing for the formation of fine patterns with improved fidelity and space uniformity by avoiding repeated spacer patterning on a single partition pattern, and controlling critical dimensions and etch profiles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If quadruple patterning is performed using repeated spacer patterning on a single partition pattern, then fine patterns with smaller critical dimensions can be formed, but pattern fidelity and space uniformity deteriorate due to unstable partition pattern profiles
Solution Approach 1:
The patent divides the patterning process into multiple independent partition patterns (first partition pattern, second partition pattern, third partition pattern) instead of repeatedly patterning a single partition. This segmentation allows each partition to be formed with stable profiles through separate photoetch processes, avoiding the cumulative instability that occurs with repeated spacer patterning on a single partition. The spaces between partitions are uniformly controlled by forming spacer sacrificial layers on each partition independently.
Solution Approach 2:
The patent introduces spacer sacrificial layers as intermediary structures formed through thermal oxidation on the surfaces of partition patterns. These spacer sacrificial layers serve as temporary mediators that define the spaces between partitions during manufacturing. After the partitions are formed, the spacer sacrificial layers are removed, leaving uniform spaces between the final fine patterns. This intermediary approach ensures space uniformity without requiring repeated patterning of unstable partition profiles.
2Ease of manufacture
If photo-exposure equipment is used for pattern formation, then manufacturing process is simplified, but the ability to form patterns with line widths smaller than 40 nm is lost due to resolution limitations
Solution Approach 1:
The patent segments the pattern formation into multiple discrete partition patterns formed through separate photoetch processes using conventional photo-exposure equipment. Each partition pattern is formed independently with stable profiles, and the final fine pattern is created by combining multiple partitions with controlled spaces between them. This segmentation allows conventional photo-exposure equipment to achieve effective line widths below its single-exposure resolution limit of 40 nm.
Solution Approach 2:
The patent transitions from single-dimension pattern formation (direct photoexposure) to multi-dimension pattern formation by creating multiple partition patterns arranged in sequence. The final fine pattern dimensions are determined by combining the dimensions of multiple partitions with the controlled spaces between them, effectively achieving sub-40 nm line widths through dimensional composition rather than direct single-step exposure.
3Manufacturing precision
If repeated spacer patterning is performed on a single partition pattern, then fine patterns can be formed, but space uniformity deteriorates due to profile instability
Solution Approach 1:
The patent segments the space definition process into independent spacer sacrificial layer formations on each partition pattern surface. Instead of repeatedly patterning a single partition, separate spacers are formed on the first, second, and third partition patterns through independent thermal oxidation processes. This segmentation ensures that each space is defined by a stable, single-step spacer formation rather than cumulative repeated patterning, maintaining space uniformity throughout the structure.
Solution Approach 2:
The patent uses thermal oxidation to create identical spacer sacrificial layers on the surfaces of different partition patterns. This copying process ensures that all spaces between partitions have uniform dimensions, as each spacer is formed by the same oxidation process under identical conditions. The uniformity is maintained because each partition receives a copied spacer structure rather than undergoing repeated variable patterning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach secures pattern fidelity and space uniformity, enabling the formation of fine patterns with larger critical dimensions and maintaining etch profile control, thus overcoming the limitations of existing technologies in micronization.
Implementation Method 1
performing an oxidation process to form a first spacer sacrificial layer over a surface of the first partition pattern
Data Source
AI summary
A method for forming a fine pattern in a semiconductor device using a quadruple patterning includes forming a first partition layer over a first material layer which is formed over a substrate, performing a photo etch process on the first partition layer to form a first partition pattern, performing an oxidation process to form a first spacer sacrificial layer over a surface of the first partition pattern, forming a second spacer sacrificial layer over the substrate structure, forming a second partition layer filling gaps between the first partition pattern, removing the second spacer sacrificial layer, performing an oxidation process to form a third spacer sacrificial layer over a surface of the second partition layer and define a second partition pattern, forming a third partition pattern filling gaps between the first partition pattern and the second partition pattern, and removing the first and third spacer sacrificial layers.