Quantile Sampling for IC Manufacturing Variability Estimation
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Solution Overview
Problem
Current methods for characterizing manufacturing variability in electronic circuits are processing-intensive and often result in inaccurate timing closure and silicon failure due to the need for extensive simulations, which can take weeks to complete, especially as device sizes shrink.
Innovation Solution
A design characterization tool that uses quantile sampling to estimate manufacturing variability characteristics by ordering samples based on predicted output values, simulating a subset of these samples to identify output distribution models, and correcting bias in the models to characterize operational variation efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If Monte Carlo sampling with extensive simulations is performed to accurately estimate manufacturing variability, then measurement precision is improved, but productivity deteriorates due to processing intensity and time consumption
Solution Approach 1:
The patent applies partial action by performing simulations on only a subset of ordered samples rather than the full Monte Carlo set. The method orders samples by predicted output values and selects a manageable subset (e.g., 100-500 samples) for actual simulation, achieving adequate accuracy without the processing burden of simulating all 10,000+ samples needed for precise statistical estimation.
Solution Approach 2:
The patent applies preliminary action by using a fast digital circuit simulator to pre-order samples based on predicted output values before performing the actual analog simulations. This preliminary ordering step allows the method to identify which samples are most critical to simulate, enabling efficient allocation of simulation resources to the most impactful cases.
2Measurement precision
If the number of simulations is increased to achieve accurate timing closure, then measurement precision is improved, but loss of time increases due to weeks of simulation time
Solution Approach 1:
The patent performs simulations on a partial set of ordered samples rather than the full Monte Carlo ensemble. By selecting a subset of samples that are most representative of the distribution tails (critical for timing closure), the method achieves adequate timing accuracy in hours rather than weeks, significantly reducing the time loss while maintaining necessary precision.
Solution Approach 2:
The patent extracts the most critical samples from the full Monte Carlo set by ordering them according to predicted output values. This extraction process identifies and isolates the subset of samples that contribute most to timing closure accuracy, allowing the method to focus computational effort on the most important cases rather than uniformly processing all samples.
3Productivity
If device size is reduced to improve integration density, then productivity is improved, but measurement precision deteriorates due to increased manufacturing variability impacts
Solution Approach 1:
The patent applies local quality by focusing simulation effort on specific regions of the parameter space that are most critical for timing closure. By ordering samples based on predicted output values and selecting those at the distribution tails, the method concentrates computational resources on the local regions that matter most for small-device timing characterization, compensating for increased variability impacts.
Solution Approach 2:
The patent changes the parameter selection criteria from uniform random sampling to ordered sampling based on predicted output values. This parameter change in the sampling strategy allows the method to adapt to increased manufacturing variability in smaller devices by focusing on the extreme cases that dominate timing closure, thereby maintaining measurement precision despite reduced device dimensions.
Data Source
AI summary
A computing system implementing a design characterization tool can sample a distribution of values for manufacturing variation of an integrated circuit described by a circuit design. The design characterization tool can order the samples based on predicted output values of the circuit design set with characteristics in the samples of the values for manufacturing variation. The computing system can implement an analog simulator to simulate the circuit design utilizing a subset of the samples of values for manufacturing variation to identify simulated output values for an output distribution model. The design characterization tool can estimate an error in the order of the samples associated with the predicted outputs of the circuit design based on the simulated output values in the output distribution model. The design characterization tool can modify the output distribution model to correct a bias based on the estimated error in the order of the samples.