Quantized Kernel Convolution Circuit for Low-Energy CNN Processing
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Solution Overview
Problem
Convolutional neural network processing hardware faces challenges with increased hardware area and energy consumption due to the need for massive multiply-and-accumulate operations and repeated use of data, particularly from higher-level memory, leading to inefficient energy usage.
Innovation Solution
An electronic apparatus that minimizes multiplication operations by using quantized kernel data stored in memory, employing operation circuits to select and accumulate output values based on identification codes, and performing convolution operations through selection and multiplication operations, reducing hardware area and energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional convolution operations are performed using massive multiply-and-accumulate operations, then processing accuracy is maintained, but hardware area and energy consumption increase significantly
Solution Approach 1:
The patent transforms the convolution operation by changing the parameter representation of kernel data from continuous weight values to discrete identification codes (0, 1, 2). This parameter transformation enables the replacement of multiplication operations with selection operations, significantly reducing energy consumption while preserving processing accuracy through the mathematical equivalence of the transformed operation.
Solution Approach 2:
The patent substitutes the mechanical multiplication operation with a selection operation based on identification codes. Instead of performing computationally intensive multiply-and-accumulate operations, the system uses lookup tables and selection circuits to achieve the same mathematical result with much lower energy consumption and hardware requirements.
2Ease of operation
If data is stored in higher-level memory (DRAM) for repeated use, then data accessibility is improved, but energy consumption increases tens to hundreds of times compared to low-level memory (SRAM)
Solution Approach 1:
The patent applies local quality by differentiating the storage requirements for different types of data. Kernel data with repeated access patterns is stored in low-level memory (SRAM) for energy efficiency, while other data can use higher-level memory. This localized optimization of memory hierarchy based on access patterns reduces overall energy consumption.
3Productivity
If kernel data is stored and repeatedly accessed from memory, then convolution operations can be performed, but hardware area increases due to connection structures for massive MAC operations
Solution Approach 1:
The patent replaces the complex mechanical connection structure required for massive multiply-and-accumulate operations with a simpler selection-based architecture. By using identification codes to index into lookup tables and selection circuits, the system achieves the same convolution processing capability with significantly reduced hardware area and simpler interconnections.
4Measurement precision
If one kernel weight is used OW×OH times and one input pixel is used FW×FH×OD times, then convolution accuracy is maintained, but energy consumption increases due to repeated memory access
Solution Approach 1:
The patent applies preliminary action by pre-processing kernel data into identification codes and storing them in lookup tables before the convolution operation. This preprocessing enables the system to perform repeated selections from pre-computed tables rather than repeatedly accessing raw kernel data from memory, significantly reducing energy consumption while maintaining convolution accuracy.
Data Source
AI summary
An electronic device and a method of controlling thereof are provided. The electronic device includes a memory configured to store coefficient data and identification code data in which kernel data is quantized; a first operation circuit configured to, based on a plurality of target elements of target data being sequentially input, select an output value corresponding to at least one of the plurality of target elements that is sequentially input according to an identification code corresponding to the one of the plurality of target elements, and accumulate the selected output value; and a second operation circuit configured to output a convolution operation result based on output data that is output from the first operation circuit and a coefficient corresponding to the output data.


