Variable-Resolution Quantizer Dithering in Multi-Bit Sigma-Delta DACs
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Solution Overview
Problem
Sigma-Delta digital-to-analog converters (DACs) produce unwanted idle tones due to the quantization process, which limit the spurious free dynamic range and signal-to-noise-and-distortion performance.
Innovation Solution
Implementing a dithering technique by adding a random or pseudo-random error signal in the Sigma-Delta modulator loop, using a multi-bit modulator with a random sequence generator and variable resolution quantizer to de-correlate and attenuate idle tones, thereby canceling them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a Sigma-Delta modulator uses a fixed resolution quantizer, then the device complexity is low, but idle tones appear at the output limiting spurious free dynamic range
Solution Approach 1:
The patent applies dynamics by making the quantizer resolution variable rather than fixed. The quantizer resolution changes over time according to a pseudo-random sequence, which dynamically modulates the quantization process. This dynamic variation in resolution breaks the periodicity that causes idle tones, effectively eliminating the harmful artifacts while maintaining acceptable device complexity through digital control mechanisms.
Solution Approach 2:
The patent changes the quantization parameter (resolution) over time according to a pseudo-random sequence. By varying the number of quantization bits dynamically, the system transforms the static quantization process into a time-varying one, which spreads the quantization noise and eliminates the correlated idle tones that appear with fixed resolution quantizers.
2Object-generated harmful factors
If dithering is applied to remove idle tones, then spurious free dynamic range improves, but device complexity increases due to additional circuitry
Solution Approach 1:
The patent merges the dithering function with the quantizer structure itself. Rather than adding separate dithering circuitry, the pseudo-random sequence is integrated into the quantization process, allowing the quantizer to perform both its primary function and the dithering function simultaneously. This consolidation achieves idle tone removal while minimizing additional device complexity.
Solution Approach 2:
The system uses its own internal resources to generate the pseudo-random sequence for dithering, rather than requiring external dither signals. The modulator structure itself generates and applies the dithering sequence, making the system self-sufficient and avoiding the need for additional external components or complex external signal generation circuitry.
Data Source
AI summary
A multi-bit (M-bit, M>1) Sigma-Delta digital-to-analog converter (DAC) with a variable resolution multi-bit quantizer that has its digital value inputs that are truncated or rounded to a resolution that follows a random or pseudo-random sequence to provide automatic dynamic dithering for removing undesired idle tones in the analog output of the Sigma-Delta DAC. Random numbers N(n) between 1 and M are provided, and M−N(n) least significant bits in each M-bit digital value at the output of the quantizer are forced to zero with a digital truncator or rounder. The random numbers N(n) may be provided by a random or pseudo-random sequence generator, e.g., Galois linear feedback shift register in combination with digital comparators and an adder.