Quantizing Circuit with Variable Reference Signals for Noisy Multi-Bit Reads
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Solution Overview
Problem
Conventional sense amplifiers struggle to accurately distinguish between small differences in voltage or current levels in multi-bit memory elements and light sensors due to noise, leading to reduced memory density and imaging device performance.
Innovation Solution
A quantizing circuit that samples electrical parameters multiple times and filters the data to reduce noise, allowing for the detection of small differences and enabling the use of multi-bit memory elements and increased sensitivity in imaging devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional sense amplifiers are used to read multi-bit memory elements, then the memory device structure is simple, but the measurement precision deteriorates due to inability to distinguish small voltage differences
Solution Approach 1:
The patent segments the quantization process into multiple sequential steps, using a counter that counts clock cycles for extended periods to resolve small voltage differences. This temporal segmentation allows the sense amplifier to accumulate measurement data over time, improving precision without requiring a more complex instantaneous comparison circuit.
Solution Approach 2:
The patent employs periodic clock cycles to repeatedly sample and integrate the voltage difference signal. By using a counter that increments with each clock cycle during the sense amplifier operation, the system performs periodic measurements that accumulate to resolve small voltage differences through temporal integration rather than instantaneous comparison.
2Quantity of substance
If multi-bit memory elements are used to increase memory density, then the storage capacity improves, but the measurement precision deteriorates due to smaller voltage level differences
Solution Approach 1:
The patent uses periodic clock cycling to repeatedly sample the voltage signal from multi-bit memory elements. The counter accumulates clock cycles based on the duration the sense amplifier output remains in a particular state, allowing temporal integration of small voltage differences that correspond to multi-bit data states, thereby maintaining measurement precision despite reduced voltage margins.
Solution Approach 2:
The patent implements feedback through the counter circuit that monitors the sense amplifier output over multiple clock cycles. The counter provides feedback about the duration and stability of the sense amplifier state, allowing the system to distinguish between different multi-bit states even when voltage differences are small, by measuring the temporal characteristics of the response.
3Measurement precision
If conventional quantization is used to maintain fast read speed, then the access time is short, but the measurement precision deteriorates due to noise susceptibility
Solution Approach 1:
The patent uses periodic clock cycles to perform multiple rapid samples of the sense amplifier output. By counting clock cycles over an extended period, the system achieves noise filtering through temporal averaging, where random noise fluctuations cancel out over many cycles, improving signal-to-noise ratio while maintaining relatively fast access times through efficient counting logic.
Solution Approach 2:
The patent performs preliminary integration of the sense amplifier signal by using the counter to accumulate clock cycles during the sense period. This preliminary action of temporal integration occurs during the normal read operation, preparing a resolved measurement value before final data output, thereby improving precision without requiring a separate measurement phase.
Data Source
AI summary
Systems, methods, and devices are disclosed, such as an integrated semiconductor device that may include a data location coupled to an electrical conductor, a delta-sigma modulator coupled to the electrical conductor, a counter coupled to an output of the delta-sigma modulator, and an interfuser coupled to an output of the counter. In some embodiments, the interfuser is configured to receive two or more counts from the counter and read data conveyed by the data location based on the two or more counts.