Quantum Addition Circuit Using Peres Gates to Reduce Carry Delay
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Solution Overview
Problem
Existing quantum computing methods for adding two n-bit numbers are inefficient in terms of computational cost, quantum cost, and delay, necessitating improved data processing methods for quantum computers.
Innovation Solution
A data processing method for quantum computers that involves a carry computing phase using Peres gate operations and controlled-NOT gate operations to compute carry bits, followed by a sum computation phase using Peres gate operations and controlled-NOT gate operations to compute sum bits, optimizing the use of ancillary qubits, quantum cost, and computational delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional quantum addition methods are used, then addition operation can be performed, but computational cost is high
Solution Approach 1:
The addition operation is divided into two distinct phases: carry computing phase and sum computation phase. This segmentation allows each phase to be optimized independently, reducing overall computational cost while maintaining productivity.
Solution Approach 2:
The carry bits are computed in advance during the carry computing phase before the sum computation phase begins. This preliminary action enables the sum computation to proceed more efficiently without carry propagation delays.
2Loss of energy
If conventional quantum addition methods are used, then addition operation can be performed, but quantum cost is high
Solution Approach 1:
The quantum circuit is segmented into carry computing and sum computation phases, allowing optimization of quantum gate usage in each phase separately, thereby reducing total quantum cost while maintaining operational efficiency.
Solution Approach 2:
Ancillary qubits are strategically used and then recovered/reset to their initial states after carrying out their computational function, reducing the net quantum resource cost while maintaining the ability to perform efficient addition operations.
3Loss of time
If conventional quantum addition methods are used, then addition operation can be performed, but delay is high
Solution Approach 1:
By separating carry computation from sum computation into distinct phases, the circuit eliminates carry propagation delays that would otherwise串行ize the entire addition operation, significantly reducing computational delay.
Solution Approach 2:
Carry bits are computed in advance during the carry computing phase, enabling the sum computation phase to proceed without waiting for carry propagation, thereby reducing overall computational delay.
4Measurement precision
If ancillary qubits are increased, then computational precision can be improved, but device complexity increases
Solution Approach 1:
Ancillary qubits are used temporarily during computation and then recovered to their initial states, allowing precise computation with minimal permanent increase in device complexity.
Solution Approach 2:
The carry computation functionality is extracted into a separate phase using dedicated ancillary qubits, allowing precise carry tracking without permanently increasing the complexity of the main quantum circuit.
Data Source
Figure 1a~1c
Figure 1d~1f
Figure 2a~2b
AI summary
A data processing method for use on a quantum computational device is proposed, which comprises, for a first n-bit element (ai)i=0,...,n-1 and a second n-bit element (bi)i=0,...,n-1 comprised in input data to be processed, performing a carry computing phase for computing a (n+1)-bit carry element (ci)i=0,...,n of carries for computing a sum of the first element (ai)i=0,...,n-1 and the second element (bi)i=0,...,n-1, which comprises: sequentially applying, for the sequence index i from 0 to n - 1, a first Peres gate operation on aι−1˜ and bι˜ to aι˜ for computing the carry bit ci of the carry element (ci)i=0,...,n, wherein bι˜ is a result of a first controlled-NOT gate operation applied to a i-th bit bi of the second element using a i-th bit ai of the first element as control element, wherein aι−1˜ is a result of a second controlled-NOT gate operation applied to a bit ai-1 of the first element using the i-th bit ai of the first element as control element, and wherein a-1 corresponds to c0 and is predefined.