Quantum Bit Array Control Gates for Dense Qubit Access

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Solution Overview

Problem

Current control structures in quantum bit arrays face challenges in accessing qubits due to their close spacing, making it difficult to integrate decoder circuits and efficiently control the qubits for large and powerful arrays.

Innovation Solution

The implementation of a quantum bit array with control structures including a control gate, pass gates, bit lines, word lines, and capacitors, which allow for selective charge flow and voltage application to control qubit operations, enabling efficient access and operation of qubits in a high-density array.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If qubits are spaced very closely together to construct large quantum bit arrays, then the density and power of the quantum system is improved, but the complexity of control structures and decoder circuits increases

Engineering Contradiction:
Improvenumber of qubitsVSAvoidcontrol structure complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent transitions from planar 2D control structures to three-dimensional vertically-stacked transistor architectures. Multiple control gates (first control gate, second control gate, third control gate) are stacked vertically above and below the qubit layer, enabling complex control functions in the vertical dimension while maintaining close horizontal spacing of qubits. This dimensional transition resolves the contradiction by accommodating more control structures without increasing lateral footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nested control structures where multiple control gates and transistor channels are stacked concentrically around the qubit layer. The first control gates are positioned above the qubit layer, second control gates below, and third control gates laterally adjacent, creating a nested configuration that maximizes control density without proportionally increasing overall system complexity.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Ease of operation

If more control structures are added to access individual qubits, then the operability and control precision is improved, but the device complexity and manufacturing difficulty increases

Engineering Contradiction:
Improvequbit access controlVSAvoiddecoder circuit integration
Core Design Contradiction:
Ease of operationVSEase of manufacture

Solution Approach 1:

The patent designs control gates with multi-functional capabilities. The same control gate structures serve multiple purposes: initializing qubit states, performing readout measurements, and executing quantum logic operations. This universality reduces the total number of distinct control structures needed, improving ease of operation while limiting the increase in manufacturing complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines multiple control functions into integrated control gate structures. Rather than separate dedicated gates for each function, the control gates are designed to perform multiple operations by applying different voltage sequences and timing patterns, thereby simplifying the overall control architecture and reducing manufacturing burden.

Inventive Principle:
Principle #5Merging (Combining)

3Length of moving object

If vertically-stacked transistor channels are used to connect bit lines to control gates, then the spacing between qubits can be reduced, but the manufacturing precision requirements increase

Engineering Contradiction:
Improvequbit spacingVSAvoidtransistor channel alignment
Core Design Contradiction:
Length of moving objectVSManufacturing precision

Solution Approach 1:

The patent segments the control structure into distinct vertically-stacked transistor channels, each with defined source and drain regions. This segmentation allows for modular fabrication processes where each transistor channel can be formed through separate processing steps, reducing the cumulative alignment precision requirements compared to forming all channels in a single complex step.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs preliminary formation of the qubit layer and insulator structures before adding the vertically-stacked transistor channels. By establishing the qubit positions and insulator layers first, subsequent transistor channel formation can be aligned to these pre-defined structures, reducing the overall manufacturing precision requirements through staged fabrication.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration allows for the construction of very large and powerful quantum bit arrays with improved control over qubit operations, enabling efficient entanglement and logic operations while maintaining voltage stability and reducing noise interference.

Implementation Method 1

a capacitor coupled to selectively store charge in the first transistor channel

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

The at least one word line selectively controls charge flow through the first transistor channel

Methodology Applied
Scientific EffectElectric Field: Electric Field

Data Source

PatentUS11723288B2Quantum bit array
Publication Date: 2023.08.08 HSU FU CHANG
  • US11723288B2 patent drawing
  • US11723288B2 patent drawing
  • US11723288B2 patent drawing

AI summary

A quantum bit array is disclosed. In an embodiment, the quantum bit array includes a control gate coupled to a qubit and at least one pass gate coupled between the qubit and an adjacent qubit to control operation of the qubit of the quantum bit array, a bit line, and a first transistor channel that connects the bit line to the control gate. The array further comprises at least one word line coupled to the first transistor channel. The at least one word line selectively controls charge flow through the first transistor channel. The array further comprises a capacitor coupled to selectively store charge in the first transistor channel.