Quantum Signal Carrier Chip With Low-Loss Capping Layer
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Solution Overview
Problem
In quantum computing, interference from qubit control and readout circuits, as well as lossy dielectrics near qubits, significantly impact the quality factor (Q) and coherence time, limiting the scalability and performance of solid-state quantum computing systems.
Innovation Solution
A multilayer wiring stack with a low-loss capping layer, formed from materials like single crystal silicon, is used to house qubit control and readout elements, allowing these elements to be electrically connected through conductive vias, thereby reducing the need for deep via etches and enhancing signal distribution without compromising coherence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If qubit control and readout circuits are placed near qubits, then signal distribution is simplified, but quality factor and coherence time deteriorate due to interference and lossy dielectrics
Solution Approach 1:
The patent divides the quantum computing system into separate functional modules: qubits are placed on a substrate while control and readout circuits are positioned on a separate carrier chip. This segmentation isolates the qubits from interfering elements, preserving quality factor while maintaining signal distribution capability through structured wiring stacks and interconnects.
Solution Approach 2:
The patent introduces a carrier chip as an intermediary component between the qubit substrate and external control systems. This carrier chip houses control and readout circuits at a distance from qubits, using wiring stacks and interconnect structures to mediate signal transmission, thereby reducing direct interference while maintaining functional connectivity.
2Ease of manufacture
If control and readout circuits are placed on the same chip as qubits, then manufacturing is simplified, but coherence time deteriorates due to lossy dielectrics near qubits
Solution Approach 1:
The patent segments the quantum system into distinct components: qubits fabricated on a substrate and control/readout circuits fabricated separately on a carrier chip. This allows each component to be optimized independently for its specific requirements while maintaining overall system functionality through standardized interconnect interfaces.
Solution Approach 2:
The patent applies different quality requirements to different regions of the system. The substrate region near qubits uses low-loss dielectric materials to preserve coherence, while the carrier chip region housing control circuits can use conventional materials. This local differentiation of material properties optimizes both coherence time and manufacturing flexibility.
3Reliability
If deep via etches are used to connect circuit elements, then electrical connection is achieved, but manufacturing complexity and signal loss increase
Solution Approach 1:
The patent transitions from vertical via etching through deep substrates to a layered wiring stack architecture where connections are made through multiple planar layers. This dimensional reorganization replaces deep vertical etches with a series of shallower lateral and vertical connections across multiple wiring layers, reducing etching complexity and signal loss.
Solution Approach 2:
The patent implements a nested wiring stack structure where multiple wiring layers are stacked vertically, with each layer containing conductors and dielectrics nested within one another. This nested architecture provides multiple routing paths and connection points, eliminating the need for single deep via etches while maintaining electrical connectivity.
Data Source
AI summary
A method of fabricating a carrier chip for distributing signals among circuit elements of a quantum computing device, includes: providing a multilayer wiring stack, the multilayer wiring stack comprising alternating layers of dielectric material and wiring; bonding a capping layer to the multilayer wiring stack, in which the capping layer includes a single crystal silicon dielectric layer; forming a via hole within the capping layer, in which the via hole extends to a first wiring layer of the multilayer wiring stack; forming an electrically conductive via within the via hole and electrically coupled to the first wiring layer; and forming a circuit element on a surface of the capping layer, in which the circuit element is directly electrically coupled to the electrically conductive via.