Quantum Chip Coupler Structure for Distant Qubit Connections
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Solution Overview
Problem
Existing quantum chip designs are limited by the presence of a carrier wafer, which restricts the use of one surface of the device wafer and hinders the connection of distant qubits.
Innovation Solution
The semiconductor device design involves removing the carrier wafer from the device wafer, allowing for the formation of a high-quality surface that can be used to connect distant qubits. This is achieved by bonding the device wafer with a top wafer and an interposer using bump bonds, and utilizing through-silicon vias (TSVs) for connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a carrier wafer is used to support the device wafer, then the device wafer can be manufactured and handled, but the carrier wafer restricts the use of one surface of the device wafer and hinders the connection of distant qubits
Solution Approach 1:
The patent removes the carrier wafer from the final device structure. The carrier wafer is used only during manufacturing and handling, then detached to expose the previously restricted surface of the device wafer for qubit connections, thereby extracting the limiting element while preserving manufacturing benefits
Solution Approach 2:
The patent divides the manufacturing and operational phases into separate structural configurations. During manufacturing, the device wafer is segmented from the final device structure and temporarily supported by the carrier wafer. After manufacturing, the carrier is removed to enable the device wafer's full functionality
2Adaptability or versatility
If the carrier wafer is removed to enable connection of distant qubits, then qubit connectivity is improved, but additional bonding structures and processes are required
Solution Approach 1:
The patent performs preliminary bonding actions during the manufacturing phase when the carrier wafer is still attached. The device wafer is pre-bonded to the interposer and top wafer structures before carrier removal, so that when the carrier is detached, the qubit connection surfaces are already prepared and positioned for immediate use
Solution Approach 2:
The patent introduces an interposer as an intermediary structure between the device wafer and the top wafer. This interposer provides a stable bonding platform that facilitates the connection of distant qubits without requiring direct complex bonding between all components, simplifying the overall assembly process
3Reliability
If bump bonds are used to bond wafers, then mechanical and electrical connections are established, but the bonding process adds manufacturing steps
Solution Approach 1:
The patent merges multiple functions into the bump bond structure. The bump bonds simultaneously provide mechanical support, electrical connectivity, and thermal management between the device wafer, interposer, and top wafer. This consolidation reduces the need for separate structures for each function, offsetting the added bonding steps with functional integration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach enables improved connectivity between qubits, enhances the performance of quantum chip devices, and provides additional chip bonding capabilities, allowing for more efficient parallel computations and better protection of qubits from spurious modes.
Implementation Method 1
A first plurality of bump bonds, located on a first side of the top wafer, bond the top wafer with the second side of the device wafer
Implementation Method 2
the bus connects the plurality of qubits via a first set of through-silicon vias (TSVs)
Data Source
AI summary
A semiconductor device includes a device wafer having a first side and a second side, a bus located on the second side of the device wafer, and a top wafer having a first side and a second side. A plurality of qubits are located on the first side of the device wafer, and a first plurality of bump bonds located on the first side of the top wafer bond the top wafer with the second side of the device wafer.