Quantum Chip Interposer Layout for Cooling and Terminal Density

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Quantum devices face limitations in cooling functionality due to the restricted number of terminals available for external wiring, which hinders the efficient cooling of quantum chips to the required temperatures necessary for optimal performance.

Innovation Solution

A quantum device design that incorporates an interposer with conductive wiring lines and a metal film on a sample stage, where the conductive wiring lines are placed on one area and the metal film for cooling is placed on a separate area, allowing for improved heat dissipation and terminal utilization without electrical short circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If the interposer uses one surface for cooling contact with the sample stage, then the quantum chip can be cooled to predetermined temperature, but the number of terminals that can be led to the outside is limited

Engineering Contradiction:
Improvecooling temperatureVSAvoidnumber of terminals
Core Design Contradiction:
TemperatureVSAdaptability or versatility

Solution Approach 1:

The interposer surface is segmented into distinct functional areas: a first area for conductive wiring lines and external terminals, and a second area for metal film cooling contact with the sample stage. This spatial segmentation allows simultaneous optimization of both terminal availability and cooling efficiency without electrical interference.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The interposer utilizes the two-dimensional surface area by dividing it into different functional zones rather than using the entire surface for a single purpose. This dimensional utilization enables both cooling functionality and terminal expansion to coexist on the same surface plane.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the quantum chip is cooled to predetermined temperature for sufficient performance, then the quantum device can operate properly, but the number of terminals must be increased which conflicts with the cooling surface area

Engineering Contradiction:
Improvequantum chip performanceVSAvoidterminal configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Different regions of the interposer are assigned different functional qualities: the first area is optimized for electrical connectivity with conductive wiring lines, while the second area is optimized for thermal management with metal film cooling contact. This local quality differentiation resolves the conflict between performance requirements and terminal complexity.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the cooling efficiency of quantum chips while maintaining a sufficient number of terminals for data acquisition, stabilizing the quantum circuit's operation at extremely low temperatures.

Implementation Method 1

the quantum chip is cooled by heat conduction with the sample stage through the interposer

Methodology Applied
Scientific EffectHeat conduction: Conduction (thermal)

Data Source

PatentUS12094812B2Quantum device having quantum chip on interposer in contact with sample stage
Publication Date: 2024.09.17 NEC CORP
  • US12094812B2 patent drawing
  • US12094812B2 patent drawing
  • US12094812B2 patent drawing

AI summary

A quantum device capable of improving a cooling effect while securing the number of terminals is provided. A quantum device according to an example embodiment includes a quantum chip 10, and an interposer 20 on which the quantum chip 10 is mounted, in which the interposer 20 includes a conductive wiring line CL1 electrically connected to the quantum chip 10, and a metal film 70 disposed in a part of the interposer 20 that is in contact with a sample stage 30 having a cooling function, and a mounting surface 21 of the interposer 20 on which the quantum chip 10 is mounted or an opposite surface 22 opposite to the mounting surface 21 includes a first area AR11 and a second area AR12 different from the first area AR11 as viewed in a direction perpendicular to the mounting surface 21 or the opposite surface 22.