Quantum Chip Interposer Layout for More Cryogenic Terminals

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Solution Overview

Problem

Existing quantum devices with interposer substrates have a limited number of terminals that can be externally drawn out, restricting their functionality and performance in cryogenic environments.

Innovation Solution

A quantum device design that includes an interposer with a first connection part for electrical connection between the interposer and quantum chip, and a second connection part on the interposer surface for a cooling plate, allowing for increased terminal output without compromising cooling performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the interposer substrate is used to mount the quantum chip, then the quantum chip can be electrically connected to the base substrate, but the number of terminals that can be externally drawn out is limited

Engineering Contradiction:
Improvenumber of terminalsVSAvoidinterposer substrate structure
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent utilizes the vertical dimension by arranging the interposer substrate between the base substrate and quantum chip in a stacked configuration. This three-dimensional arrangement allows signal lines to be drawn out from multiple locations (both the area under the quantum chip and the peripheral area), effectively increasing terminal capacity without expanding the planar footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The interposer substrate is segmented into different functional regions: a first main surface for mounting the quantum chip and establishing electrical connections, and a second main surface for drawing out signal lines. This segmentation allows independent optimization of each surface's function, enabling more terminals to be externally accessible while maintaining proper electrical connectivity.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If more terminals are drawn out from the interposer substrate, then the device functionality is enhanced, but the cooling performance may be compromised

Engineering Contradiction:
Improvedevice functionalityVSAvoidcooling performance
Core Design Contradiction:
Adaptability or versatilityVSTemperature

Solution Approach 1:

The patent applies different qualities to different regions of the interposer substrate. The area beneath the quantum chip is optimized for thermal conduction to the base substrate, while the peripheral area is optimized for signal line routing. This local differentiation allows multiple terminals to be drawn out without compromising the thermal path, as the signal lines are routed through areas not critical for heat dissipation.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The interposer substrate acts as an intermediary between the quantum chip and the external environment. It provides dedicated thermal conduction paths through its structure to the base substrate while simultaneously providing routing paths for signal lines. This intermediary role allows the system to achieve both enhanced functionality (more terminals) and maintained cooling performance by separating the thermal and electrical pathways within the interposer structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11871682B2Quantum device and method of manufacturing the same
Publication Date: 2024.01.09 NEC CORP
  • US11871682B2 patent drawing
  • US11871682B2 patent drawing
  • US11871682B2 patent drawing

AI summary

A quantum device (100) includes: an interposer (112); a quantum chip (111); a first connection part (130) that is provided between the interposer (112) and the quantum chip (111) and electrically connects a wiring layer of the interposer (112) to a wiring layer of the quantum chip (111); and a second connection part (140) that is provided on a main surface of the interposer (112) where the first connection part (130) is arranged and is connected to a cooling plate (115).