Quantum Chip Layered Interconnect for Higher Qubit Density
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Solution Overview
Problem
The integration of qubits and signal transmission lines on a quantum chip is limited by the available surface area, making it difficult to expand the number of qubits, which restricts the computing power of quantum processors.
Innovation Solution
The solution involves forming signal transmission lines and qubits on different circuit layers, with through holes in insulating substrates allowing metal pieces to connect them electrically, enabling the expansion of qubit quantity and improving integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If qubits and signal transmission lines are integrated on the same substrate surface, then the chip structure is simple, but the quantity of qubits is limited by the available surface area
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional stacked integration by placing qubits on an insulating substrate and signal transmission lines on a separate base substrate, connected through vertical through-holes. This dimensional change allows multiple qubits to be stacked vertically, dramatically increasing the quantity of qubits that can be integrated within a limited substrate area.
Solution Approach 2:
The chip is segmented into distinct functional layers: a base substrate containing signal transmission lines, an insulating substrate containing qubits, and through-holes providing vertical connections. This segmentation allows independent optimization of each layer and enables scalable expansion of qubit quantity by adding more insulating substrate layers without increasing the footprint area.
2Quantity of substance
If signal transmission lines and qubits are formed on different circuit layers, then the integration degree is improved, but the device complexity increases
Solution Approach 1:
The through-holes serve multiple functions: they provide electrical connection between layers, act as alignment references for stacking, and enable signal transmission between the base substrate and insulating substrate. This multi-functionality reduces the need for additional complex interconnection structures, thereby limiting the increase in device complexity despite the improved integration degree.
3Quantity of substance
If more qubits are integrated to increase computing power, then the computing power is improved, but the available surface area is insufficient
Solution Approach 1:
By stacking insulating substrates vertically with through-hole connections, the patent enables computing power to scale with the number of layers rather than being constrained by surface area. Each additional insulating substrate layer can host more qubits, allowing computing power to increase linearly with the number of stacked layers while maintaining a compact footprint.
Data Source
AI summary
Disclosed are a quantum chip and a fabrication method therefor. The quantum chip includes a base substrate on which signal transmission lines are formed; and at least one insulating substrate located on the base substrate, where a qubit and a through hole penetrating through the insulating substrate are formed on the insulating substrate, a metal piece is formed in the through hole, and two ends of the metal piece are electrically connected to the signal transmission lines and the qubit, respectively.