Quantum-Logic Circuit Testing Using Invariance Group Permutations

Solution Overview

Problem

Testing quantum-logic circuits is resource-intensive due to the vast number of possible states and inputs, requiring a large number of tests to verify correct operation, which is prohibitively expensive and time-consuming compared to conventional binary logic.

Innovation Solution

The method employs wreath products and invariance groups to optimize testing by dividing inputs into blocks and generating a wreath product representing an invariance group, reducing the number of necessary tests by identifying permutations that do not change the output, thus streamlining the verification process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If comprehensive testing of all possible input states is performed, then verification completeness is improved, but testing cost and time increase prohibitively

Engineering Contradiction:

Improveverification completenessVSAvoidtesting time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the quantum-logic circuit into symmetric and asymmetric portions, and further divides inputs into blocks that can be permuted. By identifying symmetric patterns, the testing process is segmented into essential tests (for asymmetric portions) and redundant tests (for symmetric portions), allowing elimination of unnecessary test cases while maintaining verification completeness.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the parameter of test case representation by using canonical forms and equivalence classes based on permutation groups. Instead of testing each individual input state separately, the method transforms the parameter space by grouping equivalent states, thereby reducing the effective number of tests needed while preserving verification reliability.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If comprehensive testing of all possible input states is performed, then verification completeness is improved, but resource consumption increases prohibitively

Engineering Contradiction:

Improveverification completenessVSAvoidtesting resources

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent segments the quantum-logic circuit into symmetric and asymmetric portions, and further divides inputs into blocks that can be permuted. By identifying symmetric patterns, the testing process is segmented into essential tests (for asymmetric portions) and redundant tests (for symmetric portions), allowing elimination of unnecessary test cases while maintaining verification completeness.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the parameter of test case representation by using canonical forms and equivalence classes based on permutation groups. Instead of testing each individual input state separately, the method transforms the parameter space by grouping equivalent states, thereby reducing the effective number of tests needed and the associated resource consumption.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If all input permutations are tested, then testing thoroughness is improved, but device complexity increases

Engineering Contradiction:

Improvetesting thoroughnessVSAvoidtesting system complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the quantum-logic circuit into symmetric and asymmetric portions, and further divides inputs into blocks that can be permuted. By identifying symmetric patterns, the testing process is segmented into essential tests (for asymmetric portions) and redundant tests (for symmetric portions), allowing elimination of unnecessary test cases while maintaining verification completeness.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent uses canonical forms as representative copies of equivalence classes of input states. Instead of working with all individual input permutations, the method creates and tests canonical representations that capture the essential behavior, thereby simplifying the testing system while maintaining thoroughness through the mathematical properties of the canonical forms.

Inventive Principle:

Principle #26Copying

Data Source

PatentUS9864954B1Optimized testing of a partially symmetric quantum-logic circuit

Publication Date: 2018.01.09 KYNDRYL INC

AI summary

A method and associated systems for using wreath products and invariance groups to test a partially symmetric quantum-logic circuits. A test system receives information that describes the architecture of a quantum-logic circuit to be tested. The system uses this information to hierarchically organize the circuit's inputs into non-overlapping blocks. The system creates set of groups associated with the blocks, and then generates an invariance group that contains one or more invariant permutations of the inputs by computing a wreath product of the set of groups. These invariant permutations identify a minimal number of tests required to verify the circuit for all possible input vectors. The system then directs a test apparatus to perform the resulting optimized test sequence upon the circuit.