Quantum Circuit Weight Reduction for Low-Noise VQE
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Solution Overview
Problem
In quantum chemical calculations using variational quantum eigensolver (VQE), noise-induced errors due to a high error rate of CNOT gates increase with the number of CNOT gates, particularly in noisy intermediate-scale quantum (NISQ) devices, affecting accuracy.
Innovation Solution
A method to reduce the weight of quantum circuits by selectively deleting Rz gates and their accompanying CNOT gates based on noise-induced error reduction, using a computer program to determine deletion targets and generate a reduced quantum circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of CNOT gates is increased to improve calculation accuracy in VQE, then measurement precision is improved, but noise-induced errors increase due to the high error rate of CNOT gates in NISQ devices
Solution Approach 1:
The patent extracts and removes specific Rz gates and their accompanying CNOT gates from the quantum circuit based on predetermined criteria. By selectively taking out these gate operations, the circuit weight is reduced while maintaining the essential computational functionality, thereby reducing noise-induced errors without significantly compromising calculation accuracy.
Solution Approach 2:
The patent changes the parameter of circuit weight by deleting Rz gates and CNOT gates. This parameter change transforms the quantum circuit from a higher-weight configuration (more gates) to a lower-weight configuration (fewer gates), reducing the cumulative noise-induced errors while preserving the variational quantum eigensolver's computational capability.
2Object-affected harmful factors
If the number of Rz gates and CNOT gates is reduced to decrease circuit weight, then noise-induced errors are reduced, but calculation accuracy may deteriorate
Solution Approach 1:
The patent applies local quality by selectively deleting Rz gates and CNOT gates based on specific criteria rather than uniformly removing all gates. The deletion is localized to specific gate operations that can be removed without compromising the overall computational accuracy, thereby reducing noise-induced errors while preserving essential calculation functionality.
Solution Approach 2:
The patent applies partial action by deleting only a subset of Rz gates and CNOT gates rather than removing all gates. This partial deletion reduces circuit weight and noise-induced errors while maintaining sufficient computational accuracy through the retention of essential gate operations.
3Device complexity
If quantum circuit optimization techniques such as Pauli term merging and quantum resource re-embedding are applied, then device complexity is reduced, but the reduction in circuit weight is limited compared to direct deletion methods
Solution Approach 1:
The patent directly extracts and removes Rz gates and CNOT gates from the quantum circuit based on predetermined criteria. This direct extraction method achieves more significant circuit weight reduction compared to conventional optimization techniques like Pauli term merging and quantum resource re-embedding, thereby improving productivity while reducing device complexity.
Solution Approach 2:
Instead of applying conventional optimization techniques that work around the circuit structure (Pauli term merging, quantum resource re-embedding), the patent inverts the approach by directly deleting specific gates based on criteria. This inverted approach achieves more efficient circuit weight reduction and improves productivity.
Data Source
AI summary
A processing unit acquires first quantum circuit information representing a first quantum circuit that includes a plurality of Rz gates and a plurality of groups of CNOT gates, each group accompanying a corresponding one of the plurality of Rz gates, and that is used for VQE, and the number of Rz gates for each angle parameter. The processing unit determines deletion target Rz gates from the plurality of Rz gates included in the first quantum circuit based on the first quantum circuit information and the number of Rz gates. The processing unit generates second quantum circuit information representing a second quantum circuit obtained by deleting the determined Rz gates and CNOT gates accompanying the determined Rz gates from the first quantum circuit. The processing unit outputs the second quantum circuit information.