Quantum Compiler SWAP Gate Routing for Restricted Connectivity
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Solution Overview
Problem
Current quantum computing technologies face challenges in executing quantum circuits due to restricted hardware connectivity between physical qubits, leading to increased SWAP gates and circuit depth, which can result in errors and reduced efficiency.
Innovation Solution
A computer-implemented method for compiling quantum circuits that involves identifying a mapping between logical and physical qubits and iteratively incorporating SWAP gates to reduce the distance between gates, thereby optimizing the number of SWAP gates and circuit depth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If SWAP gates are inserted to overcome hardware connectivity restrictions, then qubit routing is enabled, but the number of SWAP gates increases leading to higher error rates and reduced efficiency
Solution Approach 1:
The patent applies preliminary action by performing qubit routing and SWAP gate insertion during the compilation phase before quantum circuit execution. The compiler proactively maps logical qubits to physical qubits and pre-inserts necessary SWAP gates to satisfy hardware connectivity constraints, thereby enabling efficient qubit routing while minimizing the number of SWAP gates to reduce error rates during actual quantum computation
2Adaptability or versatility
If SWAP gates are inserted to enable interactions between non-adjacent qubits, then hardware connectivity restrictions are overcome, but circuit depth increases reducing computational efficiency
Solution Approach 1:
The patent applies preliminary action by performing qubit routing and SWAP gate insertion during the compilation phase before quantum circuit execution. The compiler proactively maps logical qubits to physical qubits and pre-inserts necessary SWAP gates to satisfy hardware connectivity constraints, thereby enabling efficient qubit routing while minimizing the number of SWAP gates to reduce error rates during actual quantum computation
Solution Approach 2:
The patent applies parameter changes by optimizing the routing strategy to minimize key parameters such as the number of SWAP gates and circuit depth. The compiler adjusts qubit mapping and gate insertion parameters to achieve an optimal balance between satisfying hardware connectivity constraints and maintaining computational efficiency
3Adaptability or versatility
If qubit routing is performed to map quantum circuit to hardware architecture, then restricted connectivity is accommodated, but exponential runtime is required making quantum advantage jeopardized
Solution Approach 1:
The patent applies mechanics substitution by replacing complex exponential-time classical routing algorithms with a quantum-inspired approach. The system uses quantum algorithms or hybrid quantum-classical methods during the compilation phase to solve the qubit routing problem, thereby reducing classical computation time and making the compilation process scalable for large quantum circuits on hardware with restricted connectivity
Data Source
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AI summary
Provided is a computer-implemented method of compiling at least a part of a quantum circuit comprising gates to be performed on logical qubits to a quantum processing unit architecture having physical qubits with restricted hardware connectivity, the method comprising: identifying a mapping between the logical qubits and the physical qubits and compiling an initial subset of the gates of the quantum circuit; and identifying a routing of at least the part of the quantum circuit that iteratively incorporates SWAP gates reducing a distance between an iteration subset of the gates. Provided is also a quantum compiler configured to implement the above method as well as a quantum computer having a quantum processing unit architecture having physical qubits with restricted hardware connectivity, the quantum computer configured to execute a quantum circuit compiled according to the above method.