Quantum Device Socket Ground Probe Thermal Contact

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Solution Overview

Problem

The existing quantum devices face limitations in cooling efficiency and terminal connection reliability, especially when cooled to extremely low temperatures, due to stress and strain caused by volume changes, which restricts the number of terminals that can be externally connected.

Innovation Solution

A quantum device design incorporating a quantum chip with a superconducting circuit, an interposer with through vias, and a socket with probe pins, where the socket's housing has a metal layer covering the inner walls of ground probe pin openings for enhanced thermal contact and a separate metal layer on the housing surfaces, allowing for improved cooling and increased terminal connectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If the quantum chip is cooled to extremely low temperature, then cooling efficiency is improved, but terminal connection reliability deteriorates due to stress and strain from volume changes

Engineering Contradiction:
Improvecooling efficiencyVSAvoidterminal connection reliability
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The patent divides the interposer into multiple segments along the cooling direction, with each segment having independent terminals. This segmentation allows each terminal to independently accommodate thermal expansion/contraction stresses, preventing stress concentration that would otherwise cause terminal breakage during cooling to extremely low temperatures.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the structural parameters of the interposer by introducing through-vias that extend across multiple segments. These through-vias provide mechanical reinforcement and stress distribution paths, allowing the structure to maintain terminal connection reliability while undergoing thermal contraction during cooling.

Inventive Principle:
Principle #35Parameter changes

2Temperature

If one surface of the interposer is used for cooling by a sample stage, then cooling function is achieved, but the number of terminals for external connection is limited

Engineering Contradiction:
Improvecooling functionVSAvoidnumber of terminals
Core Design Contradiction:
TemperatureVSQuantity of substance

Solution Approach 1:

The patent transitions from a two-dimensional terminal arrangement (on a single surface) to a three-dimensional structure by extending terminals through the interposer thickness via through-vias. This allows terminals to be accessed from both the top and bottom surfaces, effectively doubling the available terminal count while maintaining the single-surface cooling configuration.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

By dividing the interposer into multiple segments stacked along the cooling direction, the patent creates multiple surfaces that can each provide external terminal connections. This segmentation strategy increases the total number of accessible terminals without requiring expansion of the cooling surface area.

Inventive Principle:
Principle #1Segmentation

3Quantity of substance

If the interposer is made larger to accommodate more terminals, then terminal connectivity increases, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improveterminal connectivityVSAvoiddevice complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent concentrates the terminal multiplication function in specific localized regions (the through-via areas) rather than distributing it uniformly across the entire interposer. This allows for increased terminal connectivity while maintaining a compact overall device footprint and simplifying manufacturing by focusing complexity in manageable local areas.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances cooling efficiency and ensures reliable external connection of terminals, enabling the quantum device to handle a greater number of terminals while maintaining contact integrity during temperature changes.

Implementation Method 1

at least a part of the ground probe pin housed in the at least one opening being thermally in contact with first the metal layer of the inner wall of the at least one opening

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

Quantum mechanical phenomena include superposition of a plurality of states (a quantum variable can take on a plurality of different states simultaneously) and entanglement

Methodology Applied
Scientific EffectSuperposition:

Implementation Method 3

Quantum mechanical phenomena include superposition of a plurality of states and entanglement (a state in which a plurality of quantum variables are related regardless of space or time)

Methodology Applied
Scientific EffectEntanglement:

Implementation Method 4

In order to use such a quantum device in a superconducting state, it is necessary to cool the quantum device to an extremely low temperature (cryogenic temperature)

Methodology Applied
Scientific EffectCryogenic cooling: Cryogenics

Data Source

PatentUS20240065116A1Quantum device
Publication Date: 2024.02.22 NEC CORP
  • US20240065116A1 patent drawing
  • US20240065116A1 patent drawing
  • US20240065116A1 patent drawing

AI summary

A quantum device includes a quantum chip; an interposer flip chip mounting the quantum chip; and a socket including a housing has opening housing signal probe pins and ground probe pins. An inner wall of the opening housing the ground probe pin is covered with a metal layer, at least a part of the ground probe pin is thermally in contact with the metal layer of the inner wall which continues to a metal layer formed on at least a partial region of at least one of the first surface and the second surface of the housing.