Quantum Circuit Error Mitigation With Quasi-Stochastic Gate Expansion
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Solution Overview
Problem
Quantum computers face significant noise-related challenges that hinder their performance, with existing error mitigation techniques introducing additional errors, being applicable to specific gate types, requiring numerous twirling gates, and failing to account for all possible Pauli channels, thus limiting their efficiency.
Innovation Solution
A computing system and method that uses a deterministic procedure to measure mitigated outputs by implementing a quasi-stochastic instruction list recursively, allowing for error mitigation without additional errors, and enabling flexibility in gate changes, using classical and quantum computers to work together to mitigate noise through a quasi-stochastic instruction list and deterministic gate implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If error mitigation techniques are applied to suppress noise in quantum circuits, then measurement precision is improved, but device complexity increases due to additional twirling gates and circuit manipulation
Solution Approach 1:
The patent extracts and separates the error mitigation process into distinct components: noise characterization is performed separately on individual gates, and the resulting error maps are stored for later application. This allows the complex mitigation logic to be removed from the quantum circuit itself, reducing device complexity while maintaining measurement precision through post-processing correction
Solution Approach 2:
The patent performs noise characterization and error map generation as preliminary actions before the main computation. By pre-characterizing the noise properties of each gate and storing the error maps, the system avoids introducing additional complexity during the actual quantum circuit execution, while still achieving high-precision measurements through the pre-computed correction data
2Measurement precision
If error mitigation is applied to suppress noise effects, then measurement precision is improved, but loss of time increases due to additional sampling and longer circuit execution
Solution Approach 1:
The patent applies partial error mitigation by selecting and applying only the most significant error correction terms from the full error map, rather than implementing complete correction for all possible error channels. This partial application reduces the sampling overhead and circuit length requirements while still achieving sufficient measurement precision for practical applications
Solution Approach 2:
The patent enables dynamic adjustment of mitigation parameters such as the number of correction terms applied and the sampling depth based on the specific computational requirements. By allowing parameter optimization, the system can balance measurement precision against execution time and resource consumption, reducing loss of time when full precision is not required
3Reliability
If existing error mitigation techniques are used, then noise suppression is achieved, but adaptability decreases as they are applicable only to specific gate types
Solution Approach 1:
The patent creates a universal error mitigation framework that can handle multiple gate types and noise channels through a single unified approach. The system characterizes errors for each gate type individually and stores separate error maps, allowing the same mitigation infrastructure to be applied universally across different gate operations without requiring gate-specific mitigation logic
Solution Approach 2:
The patent segments the error mitigation process into gate-specific characterization steps, where each gate type is analyzed and its error map is generated independently. This segmentation allows the system to maintain noise suppression effectiveness for each specific gate type while using a unified mitigation framework, thereby achieving both reliability and adaptability across diverse quantum circuit components
4Reliability
If error correction is applied to correct errors as they occur, then reliability is improved, but device complexity increases due to qubit overhead for encoding logical qubits
Solution Approach 1:
The patent creates classical copies of the quantum error information through measurement and classical post-processing. Instead of using additional physical qubits to encode logical qubits as in quantum error correction, the system measures error syndromes and applies corrections through classical computation and conditional operations, achieving reliability improvement without the qubit overhead associated with quantum error correction codes
Data Source
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AI summary
The present invention concerns a computing method and a computing system for measuring a mitigated output of a quantum circuit, the computing system (1) comprising a classical computer (5) and a quantum computer or device (3), the computing system being configured to implement the following steps: - recursively mitigating the original circuit gates and any others used for mitigation and twirling, thereby building a quasi-stochastic instruction list (23) composed of sequences of gates and/or channels corresponding to the mitigated circuit, and implementing recursive expansions for said quasi-stochastic instruction list to obtain a set of corresponding deterministic circuit lists (25), - repeatedly executing the set of deterministic circuit lists on the quantum computer or device (3), returning a set of corresponding measurement outputs, and - estimating a mitigated output (〈Ô〉M) by combining said set of measurement outputs.