Matched Quantum Feedback DACs for Low-Noise Delta-Sigma ADCs
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Solution Overview
Problem
Delta-sigma analog-to-digital converters face challenges in achieving high performance due to limitations in quantization noise suppression and clock rate, particularly in the feedback mechanism of superconducting circuits, which affect the accuracy and speed of comparator decision times.
Innovation Solution
The use of matched quantum accurate digital-to-analog converters (DACs) in a bipolar configuration within the feedback loop of superconducting delta-sigma modulators, enabling time-interleaved feedback and balanced gain to enhance clocking rates and reduce quantization noise, allowing for inductive coupling and multi-bit output generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional feedback DACs are used in superconducting delta-sigma modulators, then device complexity is reduced, but quantization noise suppression and clocking rates are limited
Solution Approach 1:
The feedback DAC is segmented into multiple parallel sub-DACs (e.g., two 2-bit sub-DACs) that operate in a time-interleaved manner. Each sub-DAC handles a portion of the feedback signal at different time slots, enabling higher effective clocking rates and improved quantization noise suppression while keeping each individual sub-DAC relatively simple
Solution Approach 2:
The system employs periodic time-interleaved operation where matched quantum accurate DACs are activated in alternating time slots. This periodic activation pattern enables the feedback mechanism to operate at higher effective rates by distributing the clocking demand across multiple periodic cycles, thereby improving quantization noise suppression without requiring a single complex high-speed DAC
2Productivity
If higher clocking rates are implemented, then productivity increases, but quantization noise and comparator decision time accuracy deteriorate
Solution Approach 1:
By dividing the high-rate feedback into multiple lower-rate parallel sub-DACs operating in time-interleaved fashion, the system achieves high effective clocking rates while each individual sub-DAC operates at manageable speeds, maintaining accuracy and reducing quantization noise
Solution Approach 2:
Multiple quantized output streams from parallel sub-DACs are merged through a summation node to reconstruct the high-rate feedback signal. This merging process combines the contributions of multiple accurate low-rate converters to achieve high effective productivity while maintaining quantization noise performance
3Measurement precision
If matched quantum accurate DACs are used in bipolar configuration, then quantization noise suppression improves, but device complexity and circuit balance requirements increase
Solution Approach 1:
The bipolar configuration uses asymmetric positive and negative feedback paths with matched quantum accurate DACs having gains of +(M+1)Φ0 and -MΦ0 respectively. This asymmetric design around the implicit -Φ0 feedback from the comparator enables precise quantization noise suppression while maintaining circuit balance through deliberate gain differentiation
Solution Approach 2:
The bipolar configuration employs counterbalancing positive and negative feedback paths where matched quantum accurate DACs provide equal but opposite feedback signals. This counterweight approach cancels quantization noise through differential operation, with the asymmetric gains +(M+1) and -M providing precise balance around the comparator's implicit feedback
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves improved quantization noise suppression, enabling higher clocking rates and better signal-to-noise ratios, thereby advancing the performance of delta-sigma ADCs beyond the state of the art, suitable for advanced applications like broadband digitization of the spectrum for space-based electronic surveillance.
Implementation Method 1
a quantum comparator formed by two series Josephson junctions 13 and 14... Junctions 13 and 14 constitute a Josephson comparator that produces a digital output 16 in the form of a bit stream of binary ones and zeroes, with a binary one defined as a voltage pulse (or single-pulse quantum) generated by a Josephson junction
Implementation Method 2
An analog input signal 11 is inductively coupled through an inductor 12 to a quantum comparator formed by two series Josephson junctions 13 and 14
Data Source
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AI summary
A second order superconductor delta-sigma analog-to-digital modulator having an input for receiving an analog signal, a first integrator coupled to the input, a second integrator cascaded with the first integrator, and a quantum comparator digitizing output from the second integrator reduces quantization noise by providing matched quantum accurate DACs in a feedback loop between output from the quantum comparator and input to the first integrator. The matched quantum accurate feedback DACs produce identically repeatable voltage pulses, may be configured for multi-bit output, may be time-interleaved to permit higher clocking rates, and may be employed in a balanced bipolar configuration to allow inductive input coupling. Bipolar feedback is balanced when gain of a first DAC exceeds gain of a matched, opposite polarity DAC by the amount of implicit feedback from the comparator into the second integrator.