Quantum Gate Restricted Evolution for Low-Overhead Error Mitigation
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Solution Overview
Problem
Existing error mitigation techniques for quantum computers require exponential sampling overhead and runtime, making them impractical for larger systems and often produce inaccurate results, while methods like zero-noise extrapolation and probabilistic error cancellation are computationally expensive or biased.
Innovation Solution
A method for error mitigation in quantum computing devices through restricted evolution (EMRE) involves generating quasi-probabilistic decompositions of quantum gates, replacing them with implementable gates based on positive components, and executing the updated circuit multiple times to generate an average expectation value in constant runtime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing error mitigation techniques (zero-noise extrapolation or probabilistic error cancellation) are used, then error correction is achieved, but runtime and sampling overhead become exponential
Solution Approach 1:
The patent extracts and eliminates the negative component from the quasi-probabilistic decomposition of quantum gates. By representing each quantum gate as U = sB - (s-1)N and discarding the negative term -(s-1)N, the method retains only the positive component sB that can be implemented with implementable quantum gates. This extraction resolves the contradiction by removing the source of exponential overhead while maintaining acceptable error mitigation through the positive component alone.
Solution Approach 2:
The patent uses a simplified, approximate representation of quantum gates that is easier and faster to implement. Instead of using the full quasi-probabilistic decomposition requiring exponential resources, the method employs a disposable approximation using only implementable gates from a finite set. This approximate approach trades some precision for dramatically reduced runtime, making error mitigation practical for near-term quantum devices.
2Reliability
If existing error mitigation techniques are used, then error correction is achieved, but sampling overhead becomes exponential
Solution Approach 1:
The patent extracts and eliminates the negative component from the quasi-probabilistic decomposition of quantum gates. By representing each quantum gate as U = sB - (s-1)N and discarding the negative term -(s-1)N, the method retains only the positive component sB that can be implemented with implementable quantum gates. This extraction resolves the contradiction by removing the source of exponential overhead while maintaining acceptable error mitigation through the positive component alone.
Solution Approach 2:
The patent changes the parameters of quantum gate representation from the full quasi-probabilistic form requiring exponential sampling to a simplified form using only implementable gates. By modifying the decomposition parameters to exclude negative components and use only gates from a finite implementable set, the method reduces sampling overhead from exponential to polynomial scaling while maintaining practical error mitigation capabilities.
3Reliability
If zero-noise extrapolation is used, then error mitigation is achieved, but the estimate becomes biased and computationally expensive
Solution Approach 1:
The patent substitutes the extrapolation mechanism of zero-noise extrapolation with a direct decomposition approach. Instead of running circuits at multiple noise levels and extrapolating results (which introduces bias), the method directly decomposes each quantum gate into implementable components U = sB - (s-1)N and executes the positive part. This substitution eliminates the biased extrapolation step while providing more direct and accurate expectation value estimates through the implementable gate representation.
Data Source
AI summary
A method for mitigating error in a quantum computing device can include receiving a quantum circuit configuration including a plurality of quantum gates, and generating a plurality of quasi-probabilistic decompositions for the plurality of quantum gates, respectively, in which each of the plurality of quasi-probabilistic decompositions includes a positive component and a negative component. Also, the method can further include generating an updated quantum circuit configuration by replacing each of the plurality of quantum gates in the quantum circuit configuration with at least one implemental quantum gate selected from among a set of implementable quantum gates, the at least implemental quantum gate corresponding to the positive component of a corresponding quasi-probabilistic decomposition, and executing the updated quantum circuit configuration, by the quantum computing device, to generate an expectation value.