Quantum Gate Fidelity Estimation Across Non-Clifford Circuits
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Solution Overview
Problem
Existing methods for estimating the fidelity of quantum logic gates and circuits are limited in scalability and applicability, often assuming specific observables like the Porter-Thomas distribution and are restricted to Clifford gates, lacking flexibility and accuracy.
Innovation Solution
A method for estimating fidelity that involves defining random quantum circuits with varying depths and qubits, using randomly sampled single-qubit gates, and selecting observables that depend on the circuit, allowing for experimental and numerical estimation of fidelity through concentration of measure principles, enabling broader applicability and increased accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing fidelity estimation methods assume specific observables like Porter-Thomas distribution and are restricted to Clifford gates, then the estimation process is simplified, but the scalability and applicability to wider range of quantum circuits are limited
Solution Approach 1:
The patent changes the parameters of the fidelity estimation method by using circuit-dependent observables instead of fixed observables like Porter-Thomas distribution. This allows the method to adapt to different quantum circuits while maintaining a systematic estimation framework. The observable is selected based on the specific circuit being benchmarked, enabling broader applicability without requiring a complete redesign of the estimation process
Solution Approach 2:
The patent creates a universal fidelity estimation framework that can handle multiple types of quantum circuits and gates through the use of circuit-dependent observables. The same basic estimation protocol can be applied to Clifford gates, non-Clifford gates, and various circuit architectures by simply changing the observable selection, thus achieving multi-functionality without increasing fundamental complexity
2Productivity
If circuit depth d and number of qubits n are increased to benchmark larger quantum systems, then the scalability is improved, but the measurement precision and fidelity estimation accuracy become more difficult to maintain
Solution Approach 1:
The patent applies local quality by selecting observables that are specifically tailored to each circuit being benchmarked. Instead of using a one-size-fits-all observable, the method chooses circuit-dependent observables that are optimized for the specific structure, depth, and qubit count of each circuit. This local optimization maintains measurement precision even as circuit complexity increases
Solution Approach 2:
The methodology incorporates feedback by using the measured expectation values to compute fidelity estimates that can inform subsequent benchmarking decisions. The circuit-dependent observable selection is based on feedback from the circuit structure analysis, allowing the method to adapt to larger systems while maintaining accuracy through informed observable choices
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AI summary
Methods, systems and apparatus for estimating the fidelity of quantum logic gates. In one aspect, a method includes defining multiple sets of random quantum circuits; for each set of random quantum circuits: selecting an observable for each element in the set of random quantum circuits, wherein each selected observable corresponds to a respective element of the set of random quantum circuits and is dependent on the element to which it corresponds; estimating a value of a polarization parameter for the set of random quantum circuits, comprising performing a least mean squares minimization based on multiple expectation values, wherein each expectation value comprises an expectation value of a respective selected observable with respect to an output of an experimental implementation of a random quantum circuit corresponding to the respective selected observable; and processing the estimated polarization parameter values to obtain an estimate of the fidelity of the n-qubit quantum logic gate.