Quantum Gate Compilation Using Parametric XY Gates

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Solution Overview

Problem

Noisy Intermediate-Scale Quantum (NISQ) devices face limitations in computational power due to high error rates in two-qubit entangling gates and restricted connectivity between qubits, which increases circuit depth and reduces algorithm fidelity.

Innovation Solution

Implementing a more expressive gate set, such as the XY(β, θ) gate family, which allows for arbitrary entangling strength with precise control over phase β, reducing gate depth and error rates through optimized circuit implementations and calibration of a single flux pulse.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional two-qubit entangling gates are used in NISQ devices, then quantum computation can be performed, but high error rates and restricted connectivity increase circuit depth and reduce algorithm fidelity

Engineering Contradiction:
Improvegate fidelityVSAvoidcircuit depth
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by introducing a continuous parameter θ to control the entangling strength of the XY gate. By adjusting θ, the gate can operate in different regimes (from weak to strong entanglement), allowing optimization of circuit depth and fidelity for specific computational tasks. The gate implementation uses a time-dependent flux pulse with area θ, enabling precise control over the interaction strength between qubits without requiring additional hardware complexity.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If restricted connectivity between qubits is present, then device structure is simplified, but SWAP operations are required which increase circuit depth and reduce fidelity

Engineering Contradiction:
Improvealgorithm fidelityVSAvoidcircuit structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by decomposing arbitrary two-qubit unitary operations into sequences of XY gates with different θ parameters. This segmentation allows complex operations to be broken down into manageable gate sequences that can be efficiently implemented on devices with restricted connectivity, reducing the need for SWAP operations and minimizing circuit depth while maintaining high fidelity.

Inventive Principle:
Principle #1Segmentation

3Device complexity

If a comprehensive gate set is implemented to reduce circuit depth, then more gate types are needed, but calibration and control complexity increases

Engineering Contradiction:
Improvecircuit depthVSAvoidcalibration complexity
Core Design Contradiction:
Device complexityVSEase of operation

Solution Approach 1:

The patent applies universality by demonstrating that the XY gate with variable θ parameter can universalize the gate set functionality. A single XY gate implementation with adjustable entangling strength can replace multiple specialized gate types, providing a unified approach to two-qubit operations. This multi-functionality reduces calibration complexity because only one gate mechanism needs to be characterized and controlled, rather than multiple distinct gate types.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11900219B1Gate formation on a quantum processor
Publication Date: 2024.02.13 RIGETTI & CO INC
  • US11900219B1 patent drawing
  • US11900219B1 patent drawing
  • US11900219B1 patent drawing

AI summary

In a general aspect, a gate is formed for a quantum processor. In some implementations, an arbitrary program is received. The arbitrary program includes a first sequence of quantum logic gates, which includes a parametric XY gate. A native gate set is identified, which includes a set of quantum logic gates associated with a quantum processing unit. A second sequence of quantum logic gates corresponding to the parametric XY gate is identified, which includes a parametric quantum logic gate. Each of the quantum logic gates in the second sequence is selected from the native gate set. A native program is generated. The native program includes a third sequence of quantum logic gates. The third sequence of quantum logic gates corresponds to the first sequence of quantum logic gates and includes the second sequence of quantum logic gates. The native program is provided for execution by the quantum processing unit.