Quantum Chip Mask Fabrication via Dielectric Layer Segmentation

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Solution Overview

Problem

The existing mask fabrication methods for quantum chips face challenges in creating masks with target patterns when the ratio of dielectric layer thickness to line width exceeds the cutting depth-to-width ratio allowed by patterning apparatuses, leading to instability in pattern line width and difficulties in fabricating micro-components.

Innovation Solution

The method involves determining a first sublayer and a second sublayer of the dielectric layer, where the thickness of the second sublayer to the line width is within the allowed cutting depth-to-width ratio, and forming the target pattern on the second sublayer with a first pattern on the first sublayer that exposes the target pattern, allowing for accurate cutting and stabilization of the dielectric layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the photolithography method is used to fabricate masks, then the fabrication process is simple, but the pattern line width becomes unstable due to exposure accuracy limitations

Engineering Contradiction:
Improvefabrication process simplicityVSAvoidpattern line width stability
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent replaces the optical-based photolithography method with a direct-write laser method. The laser beam directly writes the pattern onto the resist material without requiring complex optical projection systems, thereby achieving both simplicity in fabrication process and high precision in pattern line width control.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Manufacturing precision

If the masking method is used to fabricate masks, then the pattern line width stability is improved, but the fabrication becomes difficult when the dielectric layer thickness to line width ratio exceeds the cutting depth-to-width ratio

Engineering Contradiction:
Improvepattern line width stabilityVSAvoidfabrication feasibility
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent segments the thick dielectric layer into multiple thinner sub-layers. By dividing the total thickness into several portions, each sub-layer's thickness-to-line-width ratio falls within the acceptable cutting depth-to-width ratio range, enabling successful pattern fabrication while maintaining the overall structural integrity of the mask.

Inventive Principle:
Principle #1Segmentation

3Strength

If a thick dielectric layer is used in the mask, then the mask structure is more robust, but the cutting depth-to-width ratio becomes too high for the patterning apparatus

Engineering Contradiction:
Improvemask structure robustnessVSAvoidcutting process complexity
Core Design Contradiction:
StrengthVSDevice complexity

Solution Approach 1:

The patent divides the thick dielectric layer into multiple sub-layers, each with thickness within the acceptable range for the patterning apparatus. This segmentation allows the robust mask structure to be fabricated without exceeding the cutting depth-to-width ratio limitation of the equipment.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a single thick dielectric layer to multiple thinner layers stacked vertically. By changing the dimensional distribution from one thick layer to several thin layers, the solution maintains the overall robustness while making each individual layer manufacturable with the given equipment constraints.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20240206349A1Mask Fabrication Method, Mask, Josephson Junction Element and Quantum Chip
Publication Date: 2024.06.20 ORIGIN QUANTUM COMPUTING TECH (HEFEI) CO LTD
  • US20240206349A1 patent drawing
  • US20240206349A1 patent drawing
  • US20240206349A1 patent drawing

AI summary

A mask fabrication method, mask, Josephson junction element, and quantum chip is provided, which belong to the field of quantum information, especially the field of quantum computing. The mask fabrication method includes: providing a dielectric layer, wherein a ratio of a thickness of the dielectric layer to a line width of a target pattern to be fabricated is greater than a cutting depth-to-width ratio allowed by a patterning apparatus; determining a first sublayer and a second sublayer of the dielectric layer, wherein a ratio of a thickness of the second sublayer to the line width of the target pattern is less than or equal to the cutting depth-to-width ratio; forming the target pattern on the second sublayer and a first pattern on the first sublayer, wherein the first pattern exposes the target pattern. The present application is capable of fabricating a mask containing the target pattern when the ratio of the provided dielectric layer thickness to the line width of the target pattern to be fabricated is greater than the cutting depth-to-width ratio allowed by the patterning apparatus.