Quantum Processor Gate Formation with Parametric XY Compilation
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Solution Overview
Problem
Noisy Intermediate-Scale Quantum (NISQ) devices face limitations in computational power due to high gate error rates and restricted connectivity between qubits, which increases circuit depth and fidelity issues, especially with two-qubit entangling gates having higher error rates compared to single-qubit rotations.
Innovation Solution
Implementing a more expressive gate set, such as the XY(β, θ) gate family, which allows for arbitrary entangling strength with precise control over phase β, reducing circuit depth and error rates by leveraging single-qubit control and abstract rotating frames, and using a composite pulse scheme that requires only a single flux pulse calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two-qubit entangling gates are used to achieve quantum computation, then quantum computational power is enabled, but gate error rates increase significantly
Solution Approach 1:
The patent applies parameter changes by continuously varying the coupling strength between qubits through flux pulse calibration. By adjusting the interaction strength parameter, the system can implement different entangling gate operations (from small-angle to π gates) using the same physical mechanism, thereby achieving computational versatility while maintaining gate fidelity through optimized coupling parameters.
Solution Approach 2:
The patent implements dynamics by using time-dependent flux pulses to modulate the coupling between qubits. The coupling strength is dynamically controlled during gate operations, allowing the system to transition from disconnected to strongly coupled states and back, enabling precise control over entangling operations while minimizing error accumulation.
2Device complexity
If restricted connectivity between qubits is used to simplify device structure, then device complexity is reduced, but circuit depth increases due to additional SWAP gates
Solution Approach 1:
The patent applies universality by designing a gate set that can implement any two-qubit entangling operation using a single calibrated flux pulse mechanism. This multi-functional approach allows the same physical interaction to serve multiple computational purposes (different gate angles and types), reducing the need for additional connectivity infrastructure and minimizing circuit depth.
Solution Approach 2:
By changing the flux pulse parameters (amplitude, duration, timing), the system can achieve different effective connectivity and coupling strengths, allowing flexible implementation of various gate operations without requiring physical reconfiguration of the device architecture.
3Manufacturing precision
If multiple flux pulse calibrations are performed to achieve precise gate control, then manufacturing precision is improved, but calibration complexity and time increase
Solution Approach 1:
The patent achieves universality in calibration by establishing a single flux pulse calibration that enables precise control over multiple different two-qubit gate operations. This single calibration point serves as a reference for generating various entangling gates with different coupling strengths, eliminating the need for separate calibrations for each gate type and significantly reducing calibration complexity.
Data Source
AI summary
In a general aspect, a gate is formed for a quantum processor. In some implementations, an arbitrary program is received. The arbitrary program includes a first sequence of quantum logic gates, which includes a parametric XY gate. A native gate set is identified, which includes a set of quantum logic gates associated with a quantum processing unit. A second sequence of quantum logic gates corresponding to the parametric XY gate is identified, which includes a parametric quantum logic gate. Each of the quantum logic gates in the second sequence is selected from the native gate set. A native program is generated. The native program includes a third sequence of quantum logic gates. The third sequence of quantum logic gates corresponds to the first sequence of quantum logic gates and includes the second sequence of quantum logic gates. The native program is provided for execution by the quantum processing unit.