Quantum Program Mapping Minimizes SWAP Gate Overhead
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Solution Overview
Problem
In the Noisy Intermediate-Scale Quantum phase, the topological structure of each quantum chip limits the implementation of double-qubit logic gates, leading to inefficient resource utilization due to the need for SWAP gates to adapt the quantum program to the chip's capabilities.
Innovation Solution
A mapping method and device for quantum programs and quantum chips that involve obtaining topological structures, determining execution timing, and adjusting the mapping relationship between logic and physical bits to minimize the number of SWAP gates, thereby optimizing resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the quantum program uses double-qubit logic gates that are not compatible with the chip's topological structure, then the programming flexibility is improved, but the resource utilization deteriorates due to the need for SWAP gates
Solution Approach 1:
The patent performs preliminary mapping of logic bits to physical bits before executing the quantum program. By pre-establishing this mapping relationship and adjusting it according to execution timing, the system prepares the quantum circuit in advance to be compatible with the chip's topological structure, thereby avoiding the need for SWAP gates during execution and improving resource utilization.
Solution Approach 2:
The patent dynamically adjusts the mapping relationship between logic bits and physical bits based on execution timing. The mapping is not fixed but adapts as the quantum program executes, allowing the system to optimize resource allocation at different stages of execution and improve overall resource utilization without compromising programming flexibility.
2Adaptability or versatility
If SWAP gates are added to adapt the quantum program to the chip's topological structure, then the compatibility with the chip is improved, but the circuit complexity increases
Solution Approach 1:
The patent performs the adaptation process in advance by pre-establishing the mapping relationship between logic bits and physical bits. This preliminary action eliminates the need to add SWAP gates during circuit construction, as the compatibility is achieved through the mapping strategy itself, thereby maintaining circuit simplicity while ensuring chip compatibility.
Solution Approach 2:
The patent introduces a mapping relationship as an intermediary between the quantum program and the chip's topological structure. This intermediary layer allows the system to translate logic gates into physically realizable operations without directly modifying the circuit structure, thereby achieving compatibility without increasing circuit complexity.
3Ease of manufacture
If the mapping relationship between logic bits and physical bits is fixed, then the implementation simplicity is improved, but the resource utilization deteriorates due to inability to optimize for execution timing
Solution Approach 1:
The patent transitions from a static mapping relationship to a dynamic one that changes with execution timing. The mapping is adjusted at different stages of quantum circuit execution, allowing the system to optimize resource allocation based on the current operational requirements while maintaining relatively simple implementation through automated mapping adjustment.
Solution Approach 2:
The patent establishes the initial mapping relationship in advance and then adjusts it based on execution timing. This two-stage approach combines the simplicity of pre-established mapping with the optimization benefits of timing-aware adjustment, achieving both ease of implementation and improved resource utilization.
Data Source
AI summary
Disclosed are a mapping method for a quantum program and a quantum chip, a quantum computer, and a computer. The method comprises: obtaining topological structures of physical bits in a quantum chip, a logic gate set of an initial quantum program, and an initial mapping relationship between logic bits and the physical bits; determining an execution timing of the logic gate set of the initial quantum program bits; according to the topological structures of physical bits and the initial mapping relationship, adjusting the mapping relationships between the logic bits and the physical bits corresponding to each logic gate so as to obtain the final mapping relationship; and according to the final mapping relationship, constructing the to-be-mapped quantum program equivalent to the initial quantum program to minimize the number of SWAP quantum logic gates in the to-be-mapped quantum program.