Low-Temperature Wafer Bonding for Quantum Dielectric Interfaces
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Solution Overview
Problem
Current methods for fabricating interlayer dielectrics in quantum computing devices result in lossy interfaces due to high temperature processing, leading to reduced quality factors and increased decoherence in quantum devices.
Innovation Solution
The method involves joining superconductor layers of wafers at temperatures below 150 °C, using ion milling and vacuum bonding to form high-quality single crystal dielectric interfaces without heat addition, which reduces diffusion and hillock formation, thereby achieving low-loss interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high temperature processing is used to join substrates and form dielectric layers, then manufacturing process is simplified and productivity is improved, but interface quality deteriorates due to diffusion and hillock formation causing lossy interfaces
Solution Approach 1:
The patent changes the temperature parameter from high temperature processing to low temperature processing (below 150°C) when joining substrate A and substrate B. This parameter change prevents thermal diffusion and hillock formation at the dielectric-superconductor interfaces, thereby maintaining high interface quality while still achieving successful wafer bonding and device fabrication.
Solution Approach 2:
The patent performs preliminary surface preparation of the dielectric layers before joining, including cleaning and surface activation processes. This preliminary action ensures that the surfaces are ready for low-temperature bonding, enabling successful interface formation without requiring high temperature processing that would cause diffusion and hillock formation.
2Manufacturing precision
If low temperature processing (below 150°C) is used to join superconductor layers, then interface quality is improved by reducing diffusion and hillock formation, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary surface preparation of the dielectric layers before joining, including cleaning and surface activation processes. This preliminary action ensures that the surfaces are ready for low-temperature bonding, enabling successful interface formation without requiring high temperature processing that would cause diffusion and hillock formation.
Solution Approach 2:
The patent uses an intermediary bonding process that operates at low temperatures, such as eutectic bonding or direct wafer bonding with surface activation. This intermediary approach allows joining of substrates without high temperature exposure, preventing thermal damage while achieving strong bonds, thus resolving the conflict between low temperature requirements and bonding effectiveness.
3Adaptability or versatility
If multiple wafer stacking is performed to increase qubit connectivity, then device functionality is improved with reduced crosstalk, but interface losses increase due to additional interfaces
Solution Approach 1:
The patent changes the temperature parameter to low temperature processing (below 150°C) for all joining operations in the multi-wafer stacking process. This ensures that each interface formed during stacking has high quality with minimal diffusion and hillock formation, thereby reducing surface losses even as the number of interfaces increases with additional wafer layers.
Solution Approach 2:
The patent performs preliminary surface preparation on all dielectric surfaces before stacking operations. This ensures that when multiple wafers are joined to create stacked architectures with increased qubit connectivity, each interface achieves high quality with minimal losses, allowing the system to benefit from enhanced connectivity without suffering from accumulated interface losses.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the quality factor of quantum devices by reducing surface losses and increasing connectivity, allowing for more qubits in 3D integrated circuits with reduced crosstalk and improved coherence.
Implementation Method 1
joining a surface of the first superconductor layer to (e.g., directly to) a surface of the second superconductor layer to form a wafer stack
Implementation Method 2
ion milling the surface of the first superconductor layer and the surface of the second superconductor layer prior to joining
Implementation Method 3
exposing the first substrate to a SF6 or XeF2 plasma, in which the first insulator layer serves as an etch stop for the dry etch
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
A method includes: providing a first wafer including a first substrate, a first insulator layer on the first substrate, and a first dielectric layer on the first insulator layer; providing a second wafer including a second substrate, a second insulator layer on the second substrate, and a second dielectric layer on the second insulator layer; forming a first superconductor layer on the first dielectric layer; forming a second superconductor layer on the second dielectric layer; joining a surface of the first superconductor layer to a surface of the second superconductor layer to form a wafer stack; and forming a third superconductor layer on exposed first surface of the first dielectric layer.