Self-Aligned Contacts for Quantum Well Transistors
Solution Overview
Problem
Forming source/drain contacts with low access resistance to the channel in quantum well transistor devices, particularly in III-V and SiGe/Ge material systems, is challenging due to poor contact quality and high external resistance, which degrades device performance.
Innovation Solution
A method for forming self-aligned contacts involves mesa isolation, deposition of source/drain metal, and a gate trench with a spacer layer to align contacts with the gate electrode, reducing external parasitic resistance and improving layout density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional contact formation methods are used in III-V and SiGe/Ge quantum well devices, then the manufacturing process is simple, but the contact resistance is high and contact quality is poor
Solution Approach 1:
The patent applies preliminary action by forming a heavily doped contact layer (n++-In0.53Ga0.47As) during the epitaxial growth process before contact formation. This pre-doped layer serves as a dedicated contact region that facilitates low-resistance metal-semiconductor contact, resolving the contradiction between achieving good contact quality and maintaining manufacturing simplicity.
Solution Approach 2:
The patent implements local quality by creating a spatially differentiated structure where only specific regions (contact regions) have heavy doping (n++), while other regions maintain the original quantum well structure. This localized modification enables good contact properties at contact points without affecting the overall device performance, addressing the contradiction between contact quality and manufacturing complexity.
2Reliability
If source/drain contacts are formed closer to the gate electrode to reduce access resistance, then external parasitic resistance decreases, but manufacturing precision requirements increase due to alignment complexity
Solution Approach 1:
The patent applies self-service through self-aligned contact formation where the contact regions are automatically positioned relative to the gate electrode using the spacer structure as a reference. The sidewall spacers formed on the gate trench define the contact positions, eliminating the need for separate alignment steps and achieving both low parasitic resistance and manufacturing simplicity.
Solution Approach 2:
The patent introduces sidewall spacers as an intermediary structure that mediates the alignment between contacts and gate electrode. These spacers serve as a physical reference that automatically defines the contact positions, reducing the direct alignment requirement and enabling precise contact placement with standard manufacturing processes.
3Reliability
If heavily doped contact layers are used to reduce contact resistance, then external resistance decreases, but device complexity increases due to additional processing steps
Solution Approach 1:
The patent merges the contact layer formation with the epitaxial growth process by incorporating the heavily doped contact layer as an integral part of the quantum well structure. This integration allows the contact regions to be formed during the same epitaxial process that creates the quantum well, reducing device complexity while maintaining low contact resistance.
Data Source
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AI summary
Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.