Quarter-Rate Clock Domain Transfer Interface with Phase Alignment
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Solution Overview
Problem
In DDR SDRAM physical interfaces, clock domain transfer of data faces challenges such as static skew and synchronicity issues due to on-chip variations, which affect timing performance.
Innovation Solution
A physical interface design utilizing multiple sampling circuits and multiplexers operating with different clock signals to generate and align sampled data signals, along with a training mechanism to control phase differences between clock signals CKCDC, CKW2, and CKW1, ensuring better timing margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional single sampling circuit design is used, then device complexity is low, but timing margin is insufficient and static skew cannot be compensated
Solution Approach 1:
The patent divides the sampling function into multiple independent sampling circuits (first sampling circuit, second sampling circuit, third sampling circuit), each operating with different clock signals. This segmentation allows independent optimization of each sampling path and enables better timing margin through distributed sampling operations, resolving the contradiction between reliability and device complexity.
Solution Approach 2:
The patent introduces multiplexers as intermediary components to select and combine signals from different sampling circuits. The first multiplexer and second multiplexer act as mediators that integrate outputs from multiple sampling circuits while maintaining timing synchronization, enabling complex timing control without proportionally increasing overall circuit complexity.
2Reliability
If multiple clock signals are used for sampling, then static skew can be compensated, but synchronicity control becomes more difficult
Solution Approach 1:
The patent implements feedback mechanisms through training sequences that enable the system to detect and compensate for phase differences between clock signals. The training sequence generation unit and phase difference adjustment unit create a closed-loop system that continuously monitors timing relationships and adjusts sampling operations to maintain synchronicity across multiple clock domains.
Solution Approach 2:
The patent performs preliminary alignment of clock signals through training sequences before actual data transfer operations. By establishing proper phase relationships during training, the system prepares the timing synchronization in advance, making subsequent data transfer operations simpler and more reliable despite using multiple clock signals.
3Productivity
If data sampling is performed at quarter-rate, then data transfer efficiency increases, but timing precision requirements become more stringent
Solution Approach 1:
The patent segments the sampling function across multiple circuits operating at different rates and phases. By distributing the sampling operations, each circuit can operate with relaxed timing requirements while collectively achieving precise quarter-rate data transfer through coordinated operation of the first, second, and third sampling circuits.
Solution Approach 2:
The patent performs preliminary timing alignment and phase synchronization through training sequences before actual quarter-rate data transfer. This preliminary action establishes accurate timing relationships in advance, allowing the system to maintain high timing precision during efficient quarter-rate operation without requiring extremely tight real-time timing constraints.
Data Source
AI summary
The present invention provides a physical layer and associated signal processing method for clock domain transfer of quarter-rate data. In the embodiments of the present invention, the quarter-rate data is processed by many sampling circuits by using a first clock signal, a second clock signal and a third clock signal, and phases of these clock signals are aligned by using a training mechanism to that the clock signals have better timing margins.