Quarter-Rate Clock Recovery with Phase Interpolation for Low-Power Links
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Solution Overview
Problem
Conventional clock recovery circuits face challenges in designing high-performance phase locked loops (PLLs) for high-speed data transmission, leading to increased power dissipation and chip area requirements, which limit data transmission speed and introduce noise and mismatch issues.
Innovation Solution
A quarter-rate clock recovery circuit that generates first, second, third, and fourth clocks with quarter frequency and specific phase differences, using a phase interpolation unit to produce additional clocks with phase differences of 45, 90, and 135 degrees, allowing for phase tracking and reduced data rate through de-multiplexing, thereby reducing the burden on the clock source and power dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high-performance phase locked loop (PLL) is designed for high-speed data transmission, then data transmission speed is improved, but power dissipation and chip area increase
Solution Approach 1:
The clock recovery function is divided into multiple independent channels (I, Q, Ib, Qb), each operating at quarter-rate. This segmentation allows parallel processing of data streams while using simpler, lower-power PLL circuits in each channel, avoiding the need for a single high-performance PLL that would consume excessive power and occupy large chip area.
Solution Approach 2:
The invention transitions from a single high-speed clock domain to a multi-channel quarter-rate clock domain. By introducing temporal and spatial dimensions through multiple channels operating in parallel at reduced clock rates, the system achieves high data transmission capacity without requiring high-frequency operation in each individual channel, thus reducing power dissipation.
2Speed
If a high-performance phase locked loop (PLL) is designed for high-speed data transmission, then data transmission speed is improved, but chip area increases
Solution Approach 1:
The clock recovery function is divided into multiple independent channels (I, Q, Ib, Qb), each operating at quarter-rate. This segmentation allows parallel processing of data streams while using simpler, lower-area PLL circuits in each channel, avoiding the need for a single high-performance PLL that would occupy large chip area.
Solution Approach 2:
Multiple quarter-rate clock channels (I, Q, Ib, Qb) are merged to handle high-speed data transmission collectively. By combining the capabilities of multiple low-frequency channels, the system achieves the equivalent throughput of a high-frequency single channel while using significantly less chip area, as each channel uses a simplified PLL design.
3Productivity
If the operating frequency is increased to achieve higher data transmission speed, then productivity is improved, but noise and mismatch issues increase
Solution Approach 1:
The invention changes the operating frequency parameter from high-speed single channel to quarter-rate multi-channel. By operating at lower frequencies in multiple channels, the system achieves the same data transmission capacity while significantly reducing noise and mismatch issues that are inherent in high-frequency operation, as lower frequencies are less susceptible to these harmful effects.
Data Source
AI summary
A quarter-rate clock recovery circuit includes a clock generator, a phase interpolation unit, a phase detector, and a controller. The clock generator generates first through fourth clocks having a quarter frequency of a data-rate of input data, the second, third and fourth clocks have phase differences of 90, 180, and 270 degrees with respect to a phase of the first clock, respectively. The phase interpolation unit performs a phase interpolation on the first through fourth clocks based on control signals to generate fifth through eighth clocks that have a quarter frequency of the data-rate of the input data, the fifth clock tracking a phase of the input data, the sixth, seventh, and eighth clocks respectively have phase differences of 45, 90, and 135 degree with respect to a phase of the fifth clock. The phase detector outputs signals corresponding to phase differences between the input data and the fifth through eighth clocks based on the input data and the fifth through eighth clocks. The controller generates the control signals to control the phase interpolation unit based on the signals output from the phase detector.