Quarter-Rate DFE With Two-Summer Loop Unrolling

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Solution Overview

Problem

Conventional quarter-rate data receivers face challenges in achieving timely feedback for decision feedback equalization (DFE) at high data rates due to propagation delays and capacitive loading, which affects the accuracy of data recovery and introduces non-linear transients that can shift the eye centering, making it difficult to implement direct feedback DFE without timing penalties.

Innovation Solution

The implementation of a two-summer approach with four unrolled first-tap DFE loops and a two-to-one multiplexer for each subsequent tap loop allows for more time to settle before the next sampling cycle, reducing propagation delays and enabling improved data recovery with smaller voltage overdrives, and permits different ISI corrections for data acquisition and edge detection without timing penalties.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional quarter-rate DFE with direct feedback is used, then feedback timing is tight, but propagation delays and capacitive loading increase, causing timing penalties and inaccurate data recovery

Engineering Contradiction:
Improvedata recovery accuracyVSAvoidfeedback timing
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the DFE feedback path into multiple parallel paths (e.g., four parallel feedback paths instead of one sequential path). Each path processes a portion of the feedback signal independently, allowing the system to overcome propagation delays by distributing the feedback load across multiple concurrent channels rather than a single sequential chain.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a single-dimensional sequential feedback approach to a multi-dimensional parallel feedback architecture. By adding the dimension of parallelism (multiple simultaneous feedback paths), the system achieves better timing performance and reduced propagation delay impact without sacrificing feedback accuracy.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Measurement precision

If more DFE taps are added to improve equalization, then ISI correction improves, but capacitive loading increases, worsening timing performance

Engineering Contradiction:
ImproveISI correction accuracyVSAvoidcapacitive loading
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent divides the multiple DFE taps into separate parallel groups, where each group is handled by a dedicated feedback path. This segmentation prevents the cumulative capacitive loading of all taps from affecting a single timing-critical path, as each parallel path manages only a subset of taps independently.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediate summing nodes or buffers in each parallel feedback path that act as mediators to isolate the capacitive loading effects. These intermediaries prevent the loading from one tap from directly affecting the timing of other taps, thereby maintaining timing performance while supporting multiple taps for improved ISI correction.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Area of stationary object

If single-summer approach is used, then area utilization is low, but multiplexing complexity and timing penalties increase

Engineering Contradiction:
Improvecircuit areaVSAvoidmultiplexing complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent merges multiple feedback paths by having them converge at common summing nodes or output stages. This merging approach allows the system to maintain the benefits of parallel processing (reduced timing penalties) while consolidating the area usage through shared resources, achieving a balance between area efficiency and timing performance.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent designs the feedback paths to be universal and reusable, where each parallel path can handle multiple taps and the summing nodes can serve multiple paths. This multi-functionality reduces the need for dedicated components for each path, thereby controlling area utilization while maintaining the parallel architecture's timing advantages.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Speed

If faster settling is achieved with larger voltage overdrives, then data sampling speed improves, but non-linear transients increase, shifting eye centering

Engineering Contradiction:
Improvedata sampling speedVSAvoideye centering accuracy
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

The patent employs periodic calibration or adjustment mechanisms that reset or re-center the eye diagram at regular intervals. This periodic action compensates for the cumulative effect of non-linear transients caused by voltage overdrives, maintaining eye centering accuracy over time while allowing faster settling during normal operation.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent uses feedback mechanisms that monitor the eye centering position and adjust the DFE tap coefficients or sampling timing dynamically. This feedback loop corrects the shifting caused by non-linear transients in real-time, allowing the system to maintain both fast settling speed and accurate eye centering.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11356304B1Quarter-rate data sampling with loop-unrolled decision feedback equalization
Publication Date: 2022.06.07 CADENCE DESIGN SYST INC
  • US11356304B1 patent drawing
  • US11356304B1 patent drawing
  • US11356304B1 patent drawing

AI summary

Various embodiments provide for quarter-rate data sampling with loop-unrolled decision feedback equalization (DFE) that uses a two-summer (e.g., two-summing node) approach. For example, some embodiments provide for quarter-rate data sampling comprising a plurality of unrolled first-tap DFE loops, and two summers and a two-to-one multiplexer for each of the other tap loops used for direct feedback (e.g., second tap, third tap, fourth tap, etc.)