Quarter-Rate MAP Detection With Mixed-State Trellis Complexity
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Solution Overview
Problem
High-speed, low-power, high-performance soft-output channel detectors for disk drives are needed to handle emerging magnetic disk drives' throughput while minimizing chip area and power consumption, as existing MAP detectors are complex and power-intensive despite offering only small performance improvements over SOVA detectors.
Innovation Solution
Implementing a soft-output detector with parallel MAP detectors operating at quarter-rate, using trellis structures with different numbers of states for forward, backward, and current branch detectors, and employing a Max-Log MAP algorithm to calculate soft-decisions efficiently, reducing complexity and increasing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a MAP detector is used to improve detection performance, then bit-error rate performance is improved, but device complexity and power consumption increase
Solution Approach 1:
The detector is divided into multiple parallel quarter-rate MAP detectors, each handling a subset of the data stream. This segmentation allows the system to achieve high throughput through parallel processing while keeping each individual detector unit simpler and more power-efficient than a single full-rate detector would require.
Solution Approach 2:
The patent employs dynamic trellis structures where the number of states can vary between forward, backward, and current branch detectors. This dynamic approach allows optimization of complexity for each stage of the detection process, balancing performance requirements with computational burden.
2Reliability
If a MAP detector is used to improve detection performance, then bit-error rate performance is improved, but power consumption increases
Solution Approach 1:
By segmenting the detection function across multiple parallel quarter-rate detectors, the patent distributes the computational load and power consumption across several lower-power units rather than concentrating it in a single high-power detector, achieving both performance and power efficiency.
Solution Approach 2:
The patent changes operational parameters by using quarter-rate sampling and varying the number of states in different detector stages, which reduces the computational complexity and corresponding power consumption while maintaining detection performance through the parallel architecture.
3Use of energy by stationary object
If the clock rate is reduced to achieve low-power operation, then power consumption decreases, but processing speed decreases
Solution Approach 1:
The patent segments the high-speed data stream into multiple parallel quarter-rate channels, allowing each channel to be processed at a lower clock rate (reducing power consumption) while the combined parallel output maintains the required overall processing throughput.
Solution Approach 2:
The patent transitions from a single high-speed processing dimension to multiple parallel lower-speed dimensions, effectively trading temporal speed for parallel spatial processing, which reduces power consumption while maintaining aggregate throughput.
4Reliability
If the number of states in the trellis is increased to improve detection accuracy, then bit-error rate performance is improved, but chip area increases
Solution Approach 1:
The patent segments the high-state trellis into multiple parallel detectors with fewer states each, distributing the total computational requirements across several smaller units, thereby achieving the same overall detection accuracy with reduced area per unit and enabling parallel implementation.
Solution Approach 2:
The patent uses dynamic state allocation where different stages (forward, backward, current branch) can use different numbers of states optimized for their specific functions, rather than uniformly using a large number of states throughout, reducing overall chip area while maintaining performance.
Data Source
AI summary
Methods and apparatus are provided for high-speed, low-power, high-performance channel detection. A soft-output detector is provided for processing a received signal, comprising: a forward detector for calculating forward state metrics; a backward detector for calculating backward state metrics; and a current branch detector for calculating a current branch metric, wherein at least two of the forward detector, the backward detector and the current branch detector employ trellis structures with a different number of states. A method is provided for processing a received signal using a soft-output detector, comprising: calculating forward state metrics using a forward detector; calculating backward state metrics using a backward detector; and calculating a current branch metric using a current branch detector, wherein at least two of the forward detector, the backward detector and the current branch detector employ trellis structures with a different number of states.