Quarter-Wave Transceiver Switch Circuit for Low-Loss CMOS RF Paths
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Solution Overview
Problem
Existing transceiver switch circuitry in CMOS technology faces challenges with high insertion loss, low linearity, and narrow bandwidth, particularly in 5G mm-wave transceivers, leading to poor Adjacent Channel Leakage Ratio (ACLR) and Error Vector Magnitude (EVM), and requires external filtering due to non-integrated impedance matching.
Innovation Solution
A transceiver switch circuitry utilizing λ/4 transmission lines and Doherty amplifiers with integrated impedance matching, incorporating quarter wavelength impedance transformers and switch circuitry to minimize insertion loss and enhance linearity, while allowing for wide bandwidth and integrated filtering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional CMOS transceiver switch circuitry is used, then the device can be integrated in standard CMOS processes, but it suffers from high insertion loss and narrow bandwidth
Solution Approach 1:
The transceiver switch is divided into separate Tx and Rx switch circuits, each optimized for its specific function. The Tx switch includes a main switch and auxiliary switch that can be independently controlled, while the Rx switch has its own dedicated circuitry. This segmentation allows each switch to be optimized for low insertion loss in its respective mode without compromising the other.
Solution Approach 2:
The patent implements dynamic switching between Tx and Rx modes using control signals that activate appropriate switch circuits based on operational state. The Tx switch and Rx switch can be dynamically enabled or disabled depending on whether transmission or reception is occurring, allowing the system to adapt to different operational requirements and minimize insertion loss accordingly.
2Ease of manufacture
If traditional CMOS transceiver switch circuitry is used, then the device can be integrated in standard CMOS processes, but it exhibits low linearity and poor ACLR
Solution Approach 1:
By separating the Tx and Rx switch circuits into distinct segments, each can be designed with specific linearization techniques. The Tx switch circuit can incorporate elements to improve linearity and ACLR performance independently from the Rx circuit, allowing optimization of each function without compromising the other.
Solution Approach 2:
The patent employs parameter changes in the switch circuit design, including adjustments to switching thresholds, control signal timing, and impedance matching parameters. These parameter optimizations are specifically tuned to improve linearity and adjacent channel leakage ratio while maintaining CMOS integration.
3Manufacturing precision
If external filtering is used, then impedance matching can be achieved, but device complexity increases and bandwidth is reduced
Solution Approach 1:
The patent merges the impedance matching function directly into the transceiver switch circuitry by integrating transmission line segments with specific characteristic impedances (Z1 and Z2) within the switch structure itself. This eliminates the need for separate external filtering components, reducing overall device complexity while maintaining precise impedance matching control.
Solution Approach 2:
The integrated transmission line segments serve multiple functions: they provide impedance matching, act as part of the switching mechanism, and enable bandwidth optimization. This multi-functionality reduces the need for separate dedicated components, thereby reducing device complexity while achieving the desired impedance matching performance.
4Power
If high power levels are delivered by power amplifier, then transmission output power increases, but voltage levels at peak output power become excessive for CMOS devices
Solution Approach 1:
The power amplifier output is segmented into multiple paths with different impedance levels. The main transmission line (Z1) handles high power delivery, while auxiliary transmission lines (Z2) provide alternative paths that can be activated selectively. This segmentation allows the system to deliver high power while distributing voltage stress across multiple pathways, preventing excessive voltage at any single point.
Solution Approach 2:
The patent employs parameter changes in the transmission line impedances (Z1 and Z2) to optimize the voltage power distribution. By carefully selecting and adjusting these impedance values, the system can deliver high output power while keeping voltage levels within safe operating limits for CMOS devices, preventing breakdown and ensuring reliable operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves low transmission and reception insertion loss, high isolation, and improved linearity, reducing the need for external components and enhancing overall transceiver performance in 5G mm-wave systems.
Implementation Method 1
λ/4 transmission lines implemented with traditional Power Amplifiers
Implementation Method 2
quarter wavelength impedance transformers
Data Source
AI summary
A transceiver switch circuitry having an antenna port, a receiver port, a first transmitter port and a second transmitter port. The transceiver switch circuitry is configured to be operable in a reception mode to allow reception signals at the antenna port to be forwarded to the receiver port, and in a transmission mode to allow transmission signals, having a center frequency with a wavelength λ, at the first transmitter port and the second transmitter port to be forwarded to the antenna port for transmission. The transceiver switch circuitry has a receive arrangement including a first λ/4 impedance transformer and a first switch circuitry configured to ground the first λ/4 impedance transformer at the receiver port in the transmission mode; and a transmit arrangement having a second λ/4 impedance transformer and a second switch circuitry configured to ground a second side of the second λ/4 impedance transformer in the reception mode.