Quasi-Adiabatic Logic Gates With Out-of-Phase Power and Clocking
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Solution Overview
Problem
Conventional CMOS logic circuits experience high peak current magnitudes during transient switching, leading to supply collapse and wastage of current as 'crowbar current' which is not utilized to charge parasitic capacitance.
Innovation Solution
The quasi-adiabatic logic gate employs sinusoidal supply signals out of phase with clock signals to modulate conductivity between supply nodes and intermediate nodes, allowing the transient switching to track the periodic supply signal, reducing high-frequency components and minimizing wastage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional CMOS logic circuits use rapid transient switching to change output states, then logic function performance is improved, but high peak current magnitudes are generated causing supply collapse and power wastage
Solution Approach 1:
The patent applies periodic action by using periodic supply signals (sinusoidal or triangular waveforms) instead of conventional DC supplies. The supply voltage varies periodically in phase with the clock signal, causing the logic gate to evaluate during specific phases (e.g., when supply is near zero). This periodic supply modulation reduces peak current magnitudes during switching transitions while maintaining logic function performance, directly resolving the contradiction between productivity and energy loss.
Solution Approach 2:
The patent changes the parameter of supply voltage from constant DC to time-varying periodic waveforms (sinusoidal or triangular). By modifying the supply voltage parameter to track the clock signal phase, the circuit achieves adiabatic switching conditions where transient currents are minimized. This parameter change allows the output to switch states without generating high peak currents, thus reducing power consumption while maintaining logic functionality.
2Loss of time
If conventional CMOS logic circuits switch output states rapidly, then response time is improved, but crowbar current is generated that does not charge parasitic capacitance
Solution Approach 1:
The periodic supply signal synchronized with the clock signal ensures that switching transitions occur when the supply voltage is at optimal phases (e.g., near zero crossing). This timing alignment allows rapid state changes to proceed without generating crowbar current, as the pullup and pulldown networks do not simultaneously conduct during the evaluation phase. The response time is maintained while energy wastage is eliminated.
Solution Approach 2:
The patent ensures continuous useful action by making the supply signal continuously track the clock signal phase throughout the entire cycle. During the evaluation phase, the supply voltage provides continuous power delivery to charge parasitic capacitance without interruption or crowbar current loss. This continuous synchronized operation eliminates energy wastage while maintaining rapid response capability.
Data Source
AI summary
Apparatus and associated methods relate to quasi-adiabatic logic gates in which at least one supply terminal receives a periodic power signal. The quasi-adiabatic logic gate is configured to perform a specific logic function operative upon one or more input signals. When the quasi-adiabatic logic gate switches the output from one logic state to another logic state, the transient switching portion of the output signal substantially tracks the periodic supply signal. Such a periodic supply signal can be one that transitions gradually between low and high voltage levels. Such periodic supply signals results in a transient switching portion of the logic signal having lower frequency components than have traditional CMOS logic gate transients. The quasi-adiabatic logic gate has a periodic clock signal that is not in phase with the periodic power signal.