Quasi-Cyclic Syndrome Decoder With Reduced Table Complexity
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Solution Overview
Problem
Existing error correction codes (ECCs) for non-volatile memory devices, such as NAND flash memory, require complex hardware implementations to provide robust data protection, which increases storage space and latency.
Innovation Solution
The implementation of a low-complexity hardware quasi-cyclic syndrome decoder that reduces the size of the standard array table by exploiting the cyclic shift property of quasi-cyclic linear codes, allowing for efficient decoding with reduced hardware requirements and minimal latency impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strong error-correction codes (ECCs) are used to provide robust data protection, then data reliability is improved, but hardware complexity and storage space requirements increase
Solution Approach 1:
The patent segments the standard array table into multiple smaller tables by dividing the syndrome space into subsets. Each subset table stores only a portion of the syndrome-coset leader pairs, reducing the memory size required in each individual table while collectively maintaining complete error correction coverage.
Solution Approach 2:
The patent introduces an additional dimension to the decoding process by using multiple tables indexed by syndrome subsets. Instead of a single large table indexed directly by syndrome, the system uses a two-level indexing structure: first selecting which table to access based on syndrome subset, then accessing the specific entry within that table, effectively distributing the storage burden across multiple dimensions.
2Reliability
If strong error-correction codes (ECCs) are used to provide robust data protection, then data reliability is improved, but storage space for ECC parity bits increases
Solution Approach 1:
The patent segments the standard array table into multiple smaller tables by dividing the syndrome space into subsets. Each subset table stores only a portion of the syndrome-coset leader pairs, reducing the memory size required in each individual table while collectively maintaining complete error correction coverage.
3Reliability
If complex hardware implementations are used for ECC, then data protection capability is improved, but latency increases
Solution Approach 1:
The patent segments the standard array table into multiple smaller tables by dividing the syndrome space into subsets. Each subset table stores only a portion of the syndrome-coset leader pairs, reducing the memory size required in each individual table while collectively maintaining complete error correction coverage.
Solution Approach 2:
The patent performs preliminary organization of syndrome-coset leader pairs into multiple subset tables during system initialization or manufacturing. This pre-processing arranges the data in a structure that enables faster runtime access by avoiding the need to search through a single large table, thus reducing decoding latency.
Data Source
AI summary
Disclosed are devices, systems and methods for providing hardware implementations of a quasi-cyclic syndrome decoder. An example method of reducing the complexity of a decoder includes receiving a noisy codeword that is a based on a transmitted codeword generated from a quasi-cyclic linear code; computing a plurality of syndromes based on the noisy codeword; selecting a first syndrome from the plurality of syndromes; generating a memory cell address as a function of the first syndrome; reading, based on the memory cell address, a coset leader corresponding to the first syndrome; and determining, based on the noisy codeword and the coset leader, a candidate version of the transmitted codeword.