Quasi-Cyclic LDPC Encoding for Long-Frame Coding Gain
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Solution Overview
Problem
Existing error correction encoding methods with low-density parity check codes face challenges in achieving a large coding gain while maintaining a simple encoding and decoding process, as increasing frame length leads to increased calculation complexity and apparatus scale, with only small improvements in coding gain when using quasi-cyclic structures.
Innovation Solution
The proposed solution involves an error correction encoding apparatus that calculates redundant data using a quasi-cyclic low-density parity check code and a cyclic addition apparatus with a shift register and exclusive OR, allowing for a longer frame length with improved coding gain without proportional increases in circuit scale, by iteratively applying the encoding process and utilizing a matrix data storing table for optimized parameter usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the frame length is increased to achieve larger coding gain, then the coding gain is improved, but the calculation complexity and apparatus scale are increased
Solution Approach 1:
The information data series is divided into multiple blocks of equal length, and separate parity bit series are calculated for each block. This segmentation allows the apparatus to handle long frame lengths through multiple shorter encoding operations rather than requiring a single complex large-scale encoder, thus achieving high coding gain while controlling apparatus scale.
Solution Approach 2:
The encoding process is performed periodically for each block of information data, with each block processed independently to generate its corresponding parity bits. This periodic block-based processing enables the system to achieve the effect of long frame length encoding through repeated application of shorter encoding operations.
2Reliability
If the frame length is increased to achieve larger coding gain, then the coding gain is improved, but the amount of calculation required is increased
Solution Approach 1:
By segmenting the information data into multiple blocks and calculating parity bits for each block separately, the total calculation amount is distributed across multiple independent encoding operations. This approach achieves the coding gain of long frame lengths while avoiding the exponentially increasing calculation complexity that would result from encoding the entire long frame as a single block.
Solution Approach 2:
Instead of performing a single complete encoding operation on the entire information series, the system performs partial encoding operations on individual blocks. Each block is encoded independently with its own parity calculation, which is computationally more efficient than performing excessive calculations on the full-length frame while achieving comparable error correction performance.
3Device complexity
If quasi-cyclic structure is used to simplify encoding and decoding processes, then the process complexity is reduced, but the coding gain improvement becomes small
Solution Approach 1:
The information data is segmented into multiple blocks, each processed independently through the quasi-cyclic encoding process. This segmentation allows the system to maintain the simplicity of quasi-cyclic structures while achieving the coding gain benefits of longer effective frame lengths through the accumulation of multiple block encodings.
Solution Approach 2:
The quasi-cyclic encoding structure serves multiple functions: it simplifies the encoding and decoding processes through its regular structure while simultaneously enabling the system to handle long frame lengths by processing multiple blocks. This multi-functionality allows the same simple structure to achieve both process simplicity and high coding gain.
Data Source
AI summary
Disclosed are an encoding apparatus for a quasi-cyclic low-density parity check code for calculating r×m-bit redundant data for information data of length k×m bits (k, m and r are positive integers), and a cyclic addition apparatus including a k×m-bit shift register and exclusive OR. With information data of a length of k×m×L bits (L≦k), a length of (r×m×(L+1)+k×m) bits is calculated as redundant data by adding redundant data of a length of r×m×L bits calculated using the encoding apparatus L times, k×m-bit data calculated by inputting the information data of a length of k×m×L bits to the cyclic addition apparatus, and r×m-bit redundant data calculated by inputting the k×m-bit data to the encoding apparatus.