Quasi-Cyclic LDPC Encoding for Co-Channel Interference Robustness
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Solution Overview
Problem
Current terrestrial TV broadcasting systems face significant co-channel interference issues, leading to white spaces where frequency reuse is not possible, resulting in deteriorated spectrum efficiency, especially in areas where timing and frequency synchronization between signals are not guaranteed.
Innovation Solution
A new Low Density Parity Check (LDPC) code with a length of 16200 and a code rate of 5/15 is developed, utilizing a specific LDPC encoding technique that efficiently performs encoding using a sequence derived from a parity check matrix, allowing for robust reception and efficient frequency reuse by dividing the LDPC codeword into systematic and parity parts, and employing a quasi-cyclic structure to reduce memory requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If terrestrial TV broadcasting uses conventional transmission technology, then coverage area is maintained, but spectrum efficiency deteriorates due to white spaces where frequency cannot be reused
Solution Approach 1:
The patent applies parameter changes by optimizing the LDPC code rate and block length parameters to achieve superior error correction performance. Specifically, the code rate of 5/15 and block length of 16200 are selected to maximize reception robustness in co-channel interference environments, directly addressing the contradiction between reliability and spectrum efficiency
Solution Approach 2:
The patent converts the harmful effect of co-channel interference into a benefit by designing an LDPC code specifically optimized for cloud transmission scenarios where signals from multiple transmitters overlap. The code transforms the previously harmful interference environment into an opportunity to demonstrate superior reception robustness, enabling frequency reuse in areas that would traditionally be white spaces
2Reliability
If LDPC code length is increased to improve error correction, then reception robustness improves, but encoding complexity and memory requirements increase
Solution Approach 1:
The patent applies segmentation by dividing the 16200-bit codeword into structured components: information bits, first parity bits, and second parity bits. This segmentation is implemented through a parity check matrix with a specific quasi-cyclic structure that allows the encoding process to be broken down into manageable steps, reducing computational complexity while maintaining strong error correction capability
Solution Approach 2:
The patent optimizes the balance between code length and complexity by selecting specific parameters: block length of 16200, code rate of 5/15, and a quasi-cyclic LDPC structure. These parameter choices achieve near-Shannon-limit performance while keeping encoding complexity manageable through the structured matrix design
3Productivity
If frequency reuse is implemented to improve spectrum efficiency, then co-channel interference increases, but reception robustness must be maintained
Solution Approach 1:
The patent directly addresses this contradiction by converting the harmful co-channel interference environment into a beneficial demonstration of the code's robustness. The LDPC code is specifically designed to thrive in cloud transmission scenarios where frequency reuse creates overlapping signals, transforming what would be a detrimental interference environment into an opportunity to achieve superior performance
Solution Approach 2:
The patent uses parameter optimization to enable frequency reuse despite co-channel interference. The code rate of 5/15 and block length of 16200 are specifically chosen to provide sufficient error correction margin to handle the interference from reused frequencies, allowing spectrum efficiency to improve while maintaining reception robustness
Data Source
AI summary
A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).