Quasi-Differential Loop Filter for Low-Power CIFF Amplifiers
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Solution Overview
Problem
Higher-order Cascade of Integrators with Feedforward summation (CIFF) structures in class-D amplifiers face challenges with increased power consumption, particularly in feedforward summing operations and pseudo-differential integrator stages, which affect efficiency and noise performance.
Innovation Solution
The use of a quasi-differential architecture with an active-RC integrator as the first integrator and Gm-C integrators in series, along with a modified CIFF structure, allows for efficient feedforward summation with reduced power consumption and improved noise performance by utilizing a virtual ground node for accurate summation and scaling of signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If higher-order CIFF structures are used in class-D amplifiers, then filtering accuracy and noise performance are improved, but power consumption increases significantly
Solution Approach 1:
The integrator is divided into two separate stages: a first integrator that processes the input signal and a second integrator that processes the feedback signal. This segmentation allows each integrator to operate independently with optimized power consumption, eliminating the need for high-power feedforward summing operations while maintaining the higher-order filtering functionality.
Solution Approach 2:
The patent transitions from a single-stage integrator architecture to a two-stage cascaded integrator architecture. This dimensional change in the signal processing path enables accurate signal summation through the cascaded structure rather than through high-power feedforward operations, thereby reducing power consumption while preserving filtering accuracy.
2Measurement precision
If pseudo-differential integrator stages are used, then noise performance is improved, but power consumption and circuit complexity increase
Solution Approach 1:
The pseudo-differential functionality is achieved by segmenting the signal path into separate first and second integrators that process different signals (input and feedback respectively). This segmentation eliminates the need for complex pseudo-differential stages while maintaining noise performance through the distributed integration architecture.
Solution Approach 2:
The first integrator serves multiple functions: it integrates the input signal, provides noise filtering, and contributes to the overall higher-order filtering response. This multi-functionality eliminates the need for separate pseudo-differential stages, reducing both power consumption and circuit complexity while maintaining noise performance.
3Manufacturing precision
If higher-order loop filters are implemented, then signal accuracy is improved, but circuit complexity and power consumption increase
Solution Approach 1:
The higher-order loop filter is implemented by segmenting the integration function across multiple cascaded integrator stages rather than using a single complex integrator. This segmentation achieves the desired signal accuracy through the cumulative effect of multiple simple integration stages, reducing individual stage complexity while maintaining overall precision.
4Manufacturing precision
If feedforward summing operations are performed, then signal summation accuracy is improved, but power consumption increases
Solution Approach 1:
The signal summation function is segmented across the cascaded integrator structure, where the first integrator processes the input signal and the second integrator processes the feedback signal. This segmentation eliminates the need for explicit feedforward summing operations, achieving accurate signal combination through the natural integration process while significantly reducing power consumption.
Data Source
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AI summary
A loop-filter comprising: a first-integrator, and one or more further-integrators. The first-integrator is an active-RC integrator, and comprises a first-integrator-input-terminal configured to receive: (i) an input-signal, and (ii) a feedback-signal; a first-integrator-first-output-terminal configured to provide a first-integrator-first-output-signal; and one or more first-integrator-further-output-terminals. Each of the one or more further-integrators is a Gm-C integrator, and they are connected in series between the first-integrator-first-output-terminal and a loop-filter-output-terminal. For a first further-integrator in the series, the further-integrator-input-terminal is configured to receive the first-integrator-first-output-signal. For any subsequent further-integrators in the series, the further-integrator-input-terminal is configured to receive: (i) the further-integrator-output-signal from the preceding further-integrator in the series; and (ii) one of the first-integrator-further-output-signals.